Coded data generation or conversion – Digital code to digital code converters – To or from particular bit symbol
Reexamination Certificate
1999-03-15
2001-07-10
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from particular bit symbol
C341S102000
Reexamination Certificate
active
06259383
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to transmitting a logic signal having n bits. In particular, the invention relates to reducing power consumption by reducing a maximum value and/or an average value of the number of bits that are varied at the time of transmission, as compared to the corresponding values for the logic signal before transmission.
2. Description of the Related Art
In a logic LSI represented by a microprocessor, there exists a plurality of logic signal lines for the data transmission with other logic circuits via input/output pins. For instance, in the processor indicated in Power PC 601 RISC Microprocessor User's Manual, a signal line of 32 bit lines as a memory address line and a signal line of 64 bit lines as a data line are used.
Particularly, the data line is useful for transmitting a data value requested by a program to an outside circuit and the content of the transmitted data can be considered a random value. A logic gate having a large driving capability is used for driving a large capacitance outside of the logic LSI, as indicated in Sugano et al, “MOS LSI Design Introduction” (Industrial Publisher, page 199).
From the aspect of the power consumption reduction of the whole logic circuit, it is important to reduce the frequency of operation of the logic gate, because the logic gate charges and discharges a large amount of electric charges. A method for reducing a glitch caused by the combination logic and a method for changing the representation of data value from 2's complement representation to an absolute value representation are known as a technique for limiting the frequency signal variation transmitted to and from a logic circuit, as indicated in page 82, of “International Solid-State Circuits Conference” (ISSCC '94, agenda).
SUMMARY OF THE INVENTION
In the data transmission to and from a logic circuit, by a logic gate having a large driving capability, a plurality of bits subject to a signal variation all at once causes a voltage drop of an electric power circuit and results in an error. From the aspect of power consumption reduction, it is desirable to reduce the number of bits that are varied at the time of the data transmission and reception.
An object of the present invention is to regulate a maximum value of the number of bits varied simultaneously during transmission to below a fixed value that is lower than that of a logic signal to be transmitted, and to thereby prevent an error operation due to a voltage drop and/or a power supply noise.
An object of the present invention is to reduce an average value of the number of bits varied simultaneously for a transmitted signal and therefore, to reduce power consumption.
To achieve the objects, the present invention: transforms a logic signal having n bits into a logic signal of m groups, wherein only k bits are varied, k and m are integer numbers, and each value of k and m is more than 1; transmits the logic signal of m groups; receives and transforms the received logic signal of m groups into a logic signal having the original n bits; so that a maximum value of the number of bits varied simultaneously at the time of transmission is k and less than n, and more particularly, k is less than n/2; and further so that the number of bits varied on the average during transmission is reduced as compared to the representation by the original n bits.
For example, when the level of each of all four data bit lines is varied for a clock period in the original signal as a maximum variation and the level of only two data bit lines is varied on the average in the original signal, the original signal is transformed so that only a maximum of two data bit lines and an average of two data bit lines is varied during transmission, according to one embodiment of the present invention. Therefore, maximum power consumption for the data transmission is reduced. A data word line is not limited to data bit lines physically separated, but, may be a plurality of data bit signals transmitted through a single bit line in a time shifted or time shared manner.
To make the signal transformation easy and make data transfer fast, it is desirable that the number of physical data bit lines for transmitting the transformed signal is greater than the number of data bit lines for the original signal, i.e. the number of transformed signal bits (e.g. y times m) is greater than n. For data transfer, a circuit for performing the signal transformation between the original signal and the transmitted signal is provided in a sending circuit block and a receiving circuit block.
For a typical example, the original signal is a level representation signal having n bits and the transmitted transformed signal is a transition representation signal having more than n bits, preferably the number of transformed signal bits is an integer multiple of n.
The original signal may represent data values to the nth power of base x and the transformed signal represent data values to the yth power of base m, wherein y is greater than n. The transformed signal uses m groups of y data bits each and information is transmitted dependent on whether or not there is a transition between the level of two values taken by respective data bits of the base m series.
As a general example, the original signal is based on the xth power of base 2 (e.g., fourth power) and represents the data value by the level of x data bit lines (e.g., four data bit lines). The transformed signal includes two groups (m=2) of y data bit lines for each group representing respective values within a maximum of the yth power of base m (e.g., one group representing upper two input bits and another group representing the lower two input bits, respectively).
Power consumption is reduced by reducing the frequency of the transmitted signal data variation as compared to the original signal. As a typical example, each group of the transmitted signal includes four data lines. Only one of the data lines of each group is varied at a time, so that based upon the possible combinations of varied data lines (four times four) there are sixteen patterns for the transmitted signal to represent an original signal having four bits, and the maximum variation of data bit lines for transmission can be set to 2.
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A. Chandrakasan et al, “A Low Power Chipset for Portable Multimedia Applications”, 1994 IEEE International Solid-State Circuits Conference, 1994, Session 5, pp. 82-83.
PowerPC 601—RISC Microprocessor User's Manual, p. 1-37.
J. Mavor et al, “Introduction to MOS LSI Design”, 1983, pp. 198-200.
Hitachi , Ltd.
Mattingly, Stranger & Malur, P.C.
Nguyen John
Young Brian
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