Logic circuit and semiconductor device

Details Logic circuit and semiconductor device Logic circuit and semiconductor device

1992-05-05

1994-05-10

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

257378, 257370, H01L 2978, H01L 2902, H03K 1902, H03K 1908

Patent

active

053110781

ABSTRACT:
In order to obtain a logic circuit capable of performing a high-speed operation, respective gates of a P-channel MOSFET (1) and an N-channel MOSFET (2) are connected to an input node (6) in common, and ends of resistors (12, 13) are connected to respective drains thereof. Respective emitters of an NPN transistor (3) and a PNP transistor (4) are connected to an output node (9) with an end of a resistor (5) in common, and ends of the resistors (12, 13) are connected to respective bases thereof. A source of the P-channel MOSFET (1) and a collector of the NPN transistor (3) are connected to a high potential point (8) in common while a source of the N-channel MOSFET (2) and a collector of the PNP transistor (4) are connected to a low potential point (40) in common respectively. Respective other ends of the resistors (5, 12, 13) are connected at a node (7) in common. Thus, the potential of an output terminal quickly fluctuates when a bipolar transistor is in an ON state.

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1990 Symposium on VLSI Circuits, Dig. of Technical Papers, pp. 91-92, M. Fujishima, et al., "Appraisal of BiCMOS from Circuit Voltage and Delay Time".
The Transactions of the Institute of Electronics, Information and Communication Engineers, vol. J73-C-II, No. 12, pp. 867-875, Dec., 1990, (With English Abstract).

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