Logic circuit and floating-point arithmetic unit

Details Logic circuit and floating-point arithmetic unit Logic circuit and floating-point arithmetic unit

1998-02-12

2000-07-04

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708205, G06F 742, G06F 700

Patent

active

060852119

ABSTRACT:
With the use of outputs of priority encoders serving as selection signals, final carry signals at respective bits in an adder can be selected as signals indicating whether or not prediction error is present. Accordingly, it is possible to detect earlier whether or not prediction error in a cancelling bit prediction circuit is present.

REFERENCES:
patent: 4926369 (1990-05-01), Hokenek et al.
patent: 5343413 (1994-08-01), Inoue
patent: 5530663 (1996-06-01), Garcia et al.
patent: 5764549 (1998-06-01), Bjorksten et al.
patent: 5771183 (1998-06-01), Makineni
patent: 5798952 (1998-08-01), Miller, Jr. et al.
patent: 5831884 (1998-11-01), Suzuki
Hokenek et al., "Leading-Zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit" IBM J. Res. Develop. 34:71-77 (1990).
Suzuki et al. "Leading-Zero Anticipatory Logic for High-speed Floating Point Addition" IEEE pp. 589-592 (1995).

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