Boots – shoes – and leggings
Patent
1990-02-15
1992-09-15
Mai, Tan V.
Boots, shoes, and leggings
G06F 750
Patent
active
051483874
ABSTRACT:
A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.
REFERENCES:
patent: 4866658 (1989-09-01), Mazin et al.
patent: 4870609 (1989-09-01), Yasui et al.
1984 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 16-17.
Chu et al., "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic," IEEE Journal of Solid State Circuits, vol. SC-22, No. 4, Aug. 1987, pp. 528-532.
The 279-th General National Convention of the Electronics and Communication Engineers Institute of Japan, pp. 2-83, 1987.
Yano et al., "A 3.8 ns CMOS 16.times.16 Multiplier Using Complementary Pass Transistor Logic", IEEE 1989 Custom integrated Circuits Conference, pp. 10.4.1-10.4.4.
Shively et al., "Cascading Transmission Gates to Enhance Multiplier Performance", IEEE Trans. on Computers, vol. C-33, No. 7, Jul. 1984, pp. 677-679.
Ishibashi Koichiro
Minato Osamu
Nakagawa Tetsuya
Shimohigashi Katsuhiro
Yano Kazuo
Hitachi , Ltd.
Mai Tan V.
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