Logic chip test system with path oriented decision making test p

Details Logic chip test system with path oriented decision making test p Logic chip test system with path oriented decision making test p

1978-11-20

1980-05-27

Smith, Jerry

Excavating

324 73R, 371 23, G06F 1104

Patent

active

042046335

ABSTRACT:
A path oriented decision making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines. For each designated possible chip fault, consisting of a stuck-high or stuck-low voltage at a node of the chip logic network, the generator provides a test pattern of signals to be applied to the input pins of each chip, so that the resulting signal at an output pin indicates whether the fault is present in the chip.

REFERENCES:
patent: 3739160 (1973-06-01), El-Hasan et al.
patent: 3761695 (1973-09-01), Eichelberger
patent: 3775598 (1973-11-01), Chao et al.
patent: 3916306 (1975-10-01), Patti
patent: 3961250 (1976-06-01), Snethen

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