Logic cell placement method in computer-aided-customization of u

Details Logic cell placement method in computer-aided-customization of u Logic cell placement method in computer-aided-customization of u

1986-07-21

1987-08-11

Lall, Parshotam S.

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364488, 357 45, G06F 1520

Patent

active

046866299

ABSTRACT:
An improved automatic placement process for placing logic cells in a universal array. Unused basic units are assigned to rows to reduce the congestion of the wiring in high congestion regions of a universal array. These assigned unused basic units are allocated among rows in a pyramidal manner. Those unused basic units allocated to a given row are distributed along that row in a manner to reduce wiring congestion. During a pair exchange portion of the placement process, quality criteria used for deciding whether to exchange two logic cells on different rows include skipped rows in a node, y-span of a node, minimizing the number of logic cells in excess of two in a node on a row, making a longest row shorter and making longer a shortest row or one which is within a tolerance of being a shortest row.

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"Automating Chip Layout" by S. Trimberger, CIT, Spectrum, Jun. 1982.
"Bipolar Circuit Design for a 5000-Circuit VLSI Gate Array" by A. H. Dansky, IBM J. Res. Develop., vol. 25, No. 3, May 1981.

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