Logic cell for field programmable gate array having optional inp

Details Logic cell for field programmable gate array having optional inp Logic cell for field programmable gate array having optional inp

1992-07-23

1994-07-19

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, H03K 19177

Patent

active

053312260

ABSTRACT:
According to the present invention, logic cells in a logic device include optional inverters on each input to the cell. This selective inversion allows the designer to use inverters without consuming resources available for other functions, and eliminates the need for output inverters. Since any number of inputs to the cell can be inverted, the cell can decode any address equally fast, and a designer can therefore rely on the time required to decode an address regardless the ratio and arrangement of 0's and 1's (inversions and noninversions) in the address. Also a signal which fans out from an output port and is inverted at some destinations and not others is handled easily with the present invention, because providing inverters on all inputs allows full flexibility.

REFERENCES:
patent: 4157480 (1979-06-01), Edwards
patent: 4706216 (1987-11-01), Carter
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4761570 (1988-08-01), Williams
patent: 4933575 (1990-06-01), Aso
patent: 5028821 (1991-07-01), Kaplinsky
Birkner, J.; Chang, A.; Chua, H. T.; Chao, A.; Gordon, K.; Kleinman, B.; Kolze, P. and Wong, R.; "A Very High-Speed Field Programmable Gate Array Using Metal-to-Metal Antifuse Programmable Elements", QuickLogic Corporation, IEEE 1991 Custom Integrated Circuits Conf., May 12, 1991.

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