Logic cell configuration processing method and program

Details Logic cell configuration processing method and program Logic cell configuration processing method and program

2011-03-22

2011-03-22

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S120000, C716S133000, C703S016000

Reexamination Certificate

active

07913211

ABSTRACT:
A logic cell configuration processing method for a CMOS semiconductor is configured in which leak current per unit width equal for P-channel and N-channel MOS transistors, by calculating a probable average leak current, which is an expected value of leak current of the P-channel MOS transistor and the N-channel MOS transistor in the logic cell based on an input signal to be input to the logic cell; comparing a contribution of the P-channel MOS transistor with a contribution of the N-channel MOS transistor to the calculated probable average leak current; deciding the P-channel MOS transistor or the N-channel MOS transistor, whichever has a greater contribution, to be a low leak type MOS transistor; and adjusting ON current of the low leak type MOS transistor to be equal to ON current of the other MOS transistor.

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