Logic block structure optimized for sum generation

Details Logic block structure optimized for sum generation Logic block structure optimized for sum generation

1996-06-17

1998-03-03

Ngo, Chuong Dinh

Boots, shoes, and leggings

36478401, G06F 750

Patent

active

057242763

ABSTRACT:
The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.

REFERENCES:
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5436574 (1995-07-01), Veenstra
patent: 5481206 (1996-01-01), New et al.
patent: 5481486 (1996-01-01), Cliff et al.
"The Programmable Logic Data Book", 1994, pp. 2-9 through 2-13, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.

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