Logic array with programmable element output generation

Details Logic array with programmable element output generation Logic array with programmable element output generation

1986-08-13

1988-09-13

Weldon, Ulysses

Communications: electrical

Systems

Portable self-contained

34082585, 307465, H04Q 100

Patent

active

047712848

ABSTRACT:
A programmable logic array having a plurality of electrically isolated input lines connected to an input circuit for providing an input signal to one of the plurality of input lines. Also included are a plurality of electrically isolated output lines positioned relative to the input lines to form an array having a plurality of non-conductive intersections. A plurality of programmable circuits, each positioned at a selected one of the intersections and interconnecting an adjacent input line, an adjacent output line and one of two output potentials that define one of two output states are provided. The programmable circuit is further connected to the input line such that when an input signal is received on the input line, the selected output potential representing one of the two output states is provided on the output line.

REFERENCES:
patent: 3573509 (1971-04-01), Crawford
patent: 4165538 (1979-08-01), Kitamura
patent: 4255670 (1981-03-01), Griffith
patent: 4276617 (1981-06-01), Le
patent: 4313106 (1982-06-01), Hsu
patent: 4430585 (1984-02-01), Kirk, Jr.
patent: 4534008 (1985-08-01), Fuchs et al.
IBM Technical Disclosure Bulletin, vol. 26, No. 12, 5/84 to J. P. Streck, entitled "Charge-Conserving Bit Line Boost Circuit".
IBM Technical Disclosure Bulletin, vol. 28, No. 9, 2/86 to M. M. Dovek et al., entitled "High Performance CMOS Logic Gate".

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