Logic array with multiple readout tables

Details Logic array with multiple readout tables Logic array with multiple readout tables

1974-12-30

1976-08-17

Malzahn, David H.

Registers

Transfer mechanism

Traveling pawl

307207, 328 92, H03K 1920

Patent

active

039756238

ABSTRACT:
This specification describes a programmable logic array (PLA) in which the readout table or OR array for the PLA is broken into two segments and the segments placed on opposite sides of the search table or AND array for the PLA. The output lines for the AND array can then be split so that outputs on one segment of those lines are fed to the OR array on one side and outputs on the other portion of those lines are fed to the OR array on the opposite side. Likewise the output lines in the OR arrays can be broken so that different functions can be fed out to opposite sides of the OR arrays. It is also possible to break input lines in both the OR and AND arrays to isolate functions from one another.

REFERENCES:
patent: 3699534 (1972-10-01), Kavtz
patent: 3761902 (1973-09-01), Weinberger
patent: 3816725 (1974-06-01), Greer
patent: 3818452 (1974-06-01), Greer
patent: 3849638 (1974-11-01), Greer

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