Logic array structure for depletion mode-FET load circuit techno

Details Logic array structure for depletion mode-FET load circuit techno Logic array structure for depletion mode-FET load circuit techno

1975-12-19

1977-07-05

James, Andrew J.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

357 23, 357 68, 357 24, 307215, 340166R, H03K 3353, H03K 1934, H01L 2978, H01L 2348

Patent

active

040342433

ABSTRACT:
A depletion mode load device structure is disclosed which improved upon the existing Weinberger layout technique, as applied to enhancement mode/depletion mode circuitry. The structure of an FET, self biased load device includes a single metallized vertical line performing three functions: a source contact for the FET device, the gate electrode for the FET device, and the output line for the circuit for which the device serves as the load. Use of this structure results in an increased horizontal circuit packing density, which is particularly useful in the decoder circuits for a programmed logic array.

REFERENCES:
patent: 3761784 (1973-09-01), Jund
patent: 3896482 (1975-07-01), Brechling
patent: 3911289 (1975-10-01), Takemoto
patent: 3916268 (1975-10-01), Engeler et al.
patent: 3943551 (1976-03-01), Skorup

Affiliated with

Also associated with

Rating

Logic array structure for depletion mode-FET load circuit techno does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic array structure for depletion mode-FET load circuit techno, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic array structure for depletion mode-FET load circuit techno will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-579698