Logic array having high frequency internal clocking

Details Logic array having high frequency internal clocking Logic array having high frequency internal clocking

1992-04-02

1993-04-20

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307269, 364716, H03K 513, H03K 1902

Patent

active

052045552

ABSTRACT:
A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.

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patent: 5075575 (1991-12-01), Shizukuishi et al.
GA23SV8/GA23S8, "High-Performance Logic Device Gallium Arsenide", Gazelle Microcircuits, Inc., pp. 1-12, Apr. 1989.
PAL20RA 10-20, "Programmable Array Logic", MMI, 5-95 to 5-102.
Am2971, "Programmable Event Generator (PEG)", pp. 4-286 to 4-303, AMD.
AmPAL*23S8, pp. 4-102 to 4-121, AMD/MMI.

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