Logic arithmetic circuit

Details Logic arithmetic circuit Logic arithmetic circuit

1986-11-24

1988-03-22

Eng, David Y.

Boots, shoes, and leggings

364200, G06F 750

Patent

active

047333650

ABSTRACT:
A logic arithmetic circuit comprising first through sixth transistors, the first through third being P-channel transistors and the fourth through sixth being N-channel transistors. The gates of the first and sixth transistors are supplied by a synchronizing signal; the gates of the second and fifth are supplied by a first operand signal; and the gates of the third and fourth are supplied by a second operand signal. Respective current paths are provided between the first and the sixth transistors through the second and fourth transistors and through the third and fifth transistors with the output signal taken at the connecting point of the fourth and fifth transistors with the sixth transistor.

REFERENCES:
patent: 4435782 (1984-03-01), Kaufman
patent: 4449197 (1984-05-01), Henry et al.
patent: 4559609 (1985-12-01), Robinson
patent: 4564921 (1986-01-01), Suganuma
patent: 4592007 (1986-05-01), Ohhashi
patent: 4601007 (1986-07-01), Uya et al.
patent: 4621338 (1986-11-01), Uhlenhoff
patent: 4667303 (1987-05-01), Pfennings
Mavor, et al., "Random Logic," Introduction to MOS LSI Design, Chapter 4, Sec. 1.1, pp. 90-92 1983.

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