Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
2001-11-23
2004-09-07
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S009000, C257S039000, C257S532000, C257S536000, C257S553000
Reexamination Certificate
active
06787795
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-357789, filed Nov. 24, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic apparatus and a logic circuit using a single-elemental device which utilizes charging effect of a single elemental charge.
2. Description of the Related Art
A conventional semiconductor integrated circuit device (LSI) is designed according to the function before manufacture, and fabricated by integrating transistors and wiring on a semiconductor chip. For this reason, after manufacture, the LSI cannot change its structure and function. For this reason, many kinds of LSI have been made according to a use.
In contrast, there have been developed a general-purpose chip including LSI such as gate array capable of adding an operation process function met for use with a user after having shipped. However, the degree of freedom of the design of the chip is extremely low. In conventional gate arrays, a user must perform a manufacturing process to form wiring for connecting gates. Therefore, semiconductor manufacturing processes such as evaporation, exposure, developing, and so on is needed. For this reason, a user must have semiconductor production facility.
From such situation, in late years, design concept as referred to as reconfigurable computing (for example, Sueyoshi et al., “information processing” vol. 40 No. 8, page 778) attracts attention as guiding principle of a system design of the next generation. This reconfigurable computing is a technology that can change an operation process function of LSI by a simple operation according to the use desired by a user, if a general purpose semiconductor chip is prepared.
The reconfigurable computing technology differs from a conventional gate array technology that it does not need a semiconductor manufacturing process such as wiring, and enables a change of a logic operation by a simple method such as changes of a program.
If LSI that the reconfigurable computing is possible can be realized, remarkable improvement of process yield can be expected by producing a small kind of basic LSI in large quantities and changing them in many kinds of functions by a simple method.
It is necessary for realizing the reconfigarable computing to provide a function that make an optimized operation store in a logical element as a minimum configuration element for performing a logic operation and rewrite it according to a use. Nonvolatile memories such as EEPROMs have been made research as a logic element to use in the configurable computing (Kume, “Oyo Butsuri” Vol. 65, No. 11, page 1114).
In a flash memory using flash memory cells as EEPROM, when electrons are injected into a floating gate electrode, the threshold of MOSFET increases. Under a certain gate bias condition, it is possible to control ON/OFF of a current by an injection state of electrons. Also, the injected charges can be removed by setting a bias condition properly.
As described above, EEPROM has been looked at as a logic element of an advanced system to which a reconfigurable computing can be applied by virtue of the programmability. However, EEPROM includes problems such as a high drive voltage and an insufficient holding time.
Further, EEPROM can control only ON/OFF of a current, so that optimization of a system (a program) must be performed by merely switching of ON/OFF of the current. For this reason, a great number of elements are required in the formation of a programmable function block.
The object of the present invention is to provide a logic device enabling a reconfigurable computing which can expect high yield by using logic elements having a low drive voltage and a good holding characteristic.
BRIEF SUMMARY OF THE INVENTION
An aspect of the invention, there is provided a logic circuit apparatus comprising: a semiconductor substrate; a first single-electron device comprising a first conductive island insulatively disposed over the semiconductor substrate, at least two first tunnel barriers insulatively disposed over the semiconductor substrate, the first conductive island being interposed between the first tunnel barriers, first and second electrodes insulatively disposed over the semiconductor substrate, the first conductive island being coupled with the first and second electrodes through the first tunnel barriers, respectively, and a first charge storage region insulatively disposed over the first conductive island; and a second single-electron device comprising a second conductive island insulatively disposed over the semiconductor substrate, at least two second tunnel barriers insulatively disposed over the semiconductor substrate, the second conductive island being interposed between the second tunnel barriers, third and fourth electrodes insulatively disposed over the semiconductor substrate, the second conductive island being coupled with the third and fourth electrodes through the second tunnel barriers, respectively, and a second charge storage region insulatively disposed over the second conductive island, the third electrode of the second-single electron device being connected to the first electrode of the first single-electron device.
REFERENCES:
patent: 5838021 (1998-11-01), Ancona
patent: 5963471 (1999-10-01), Ohata et al.
patent: 6060748 (2000-05-01), Uchida et al.
patent: 6487112 (2002-11-01), Wasshuber
Hitoshi Kume, et al., “Flash Memory Technology”, Central Research Laboratory, Hitachi Ltd., Nov. 1996, pp. 1114-1124.
T. Sueyoshi, “Reconfigurable Computing”, IPSJ Magazine, vol. 40, No. 8, Aug. 1999, pp. 777-782.
Koga Junji
Ohba Ryuji
Uchida Ken
Kabushiki Kaisha Toshiba
Thomas Tom
Warren Matthew E.
LandOfFree
Logic apparatus and logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Logic apparatus and logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic apparatus and logic circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3234763