Logic analyzer having a plurality of sampling channels

Details Logic analyzer having a plurality of sampling channels Logic analyzer having a plurality of sampling channels

1986-06-18

1987-09-29

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Plural, automatically sequential tests

324 73AT, 324121R, 371 15, 371 20, G01R 1500, G01R 3128

Patent

active

046971386

ABSTRACT:
A logic analyzer includes a plurality of data sampling channels which are operative in response to respective different clock signals independent of one another. Information of the sequence in time in which the sampled data are produced in the plurality of the sampling channels is stored in a memory for the purpose of display. To this end, each of the sampling channels is provided with a clock discriminating circuit having two inputs supplied with a common clock signal generated internally and a clock signal specific to the associated sampling channel. The outputs of all the clock discriminating circuits are stored in a memory whose contents thus indicate the sequence in time in which the data are sampled in the plurality of the sampling channels.

REFERENCES:
patent: 4195258 (1980-03-01), Yen
patent: 4364036 (1982-12-01), Shimizu
patent: 4425643 (1984-01-01), Chapman et al.
patent: 4513395 (1985-04-01), Henry et al.

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