Logic analyzer for a multiplexed digital bus

Details Logic analyzer for a multiplexed digital bus Logic analyzer for a multiplexed digital bus

1981-06-08

1984-02-28

Atkinson, Charles E.

Excavating

324 73R, 340721, 340801, 340802, 364900, 371 29, G09G 108

Patent

active

044344880

ABSTRACT:
A logic analyzer for measuring individually a plurality of logic signals transmitted via a multiplexed digital bus in a time-sharing manner is disclosed. First and second memory circuits store respectively first and second logic signals of the multiplexed digital bus in accordance with first and second strobe signals synchronized with the first and second logic signals.

REFERENCES:
patent: 3522597 (1970-08-01), Murphy
patent: 4139903 (1979-02-01), Morrill, Jr. et al.
patent: 4204114 (1980-05-01), Shoemaker et al.
patent: 4257043 (1981-03-01), Tsuchiko
patent: 4308615 (1981-12-01), Koegil et al.
patent: 4354260 (1982-10-01), Planzo
patent: 4364036 (1982-12-01), Shimizu
Farnbach, Logic State Analyzers-A New Instrument for Analyzing Sequential Digital Processes, IEEE Transactions on Instrumentation and Measurement, vol. IM-24, No. 4, Dec. 1975, pp. 353-356.

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