Logic analyzer

Details Logic analyzer Logic analyzer

1985-05-24

1987-09-22

Fleming, Michael R.

Excavating

371 29, G06F 1100

Patent

active

046960040

ABSTRACT:
Logic output data of a plurality of channels simultaneously obtained from a circuit under test are sequentially input in a memory, and after inputting a predetermined amount of such data, they are compared with corresponding expected values. The input data are divided into blocks, each including a plurality of data. Whether a mismatch is present in the comparison results for each block is indicated by a respective block element, and such block elements are displayed in a predetermined arrangement. It is also possible to provide a conventional list display including the input timing corresponding to the comparison results in which a mismatch is present.

REFERENCES:
patent: 4425643 (1984-01-01), Chapman et al.
patent: 4484329 (1984-11-01), Slamka
patent: 4546467 (1985-10-01), Yamamoto
patent: 4574354 (1986-03-01), Mihalik
patent: 4583223 (1986-04-01), Inoue
patent: 4601033 (1986-07-01), Whelan
patent: 4604746 (1986-08-01), Blum

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