Logic analysis system for logic emulation systems

Details Logic analysis system for logic emulation systems Logic analysis system for logic emulation systems

1998-08-14

2001-04-24

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

Of peripheral device

C713S400000, C714S039000, C714S724000

Reexamination Certificate

active

06223148

ABSTRACT:

BACKGROUND OF THE INVENTION
Reconfigurable or programmable logic devices are a general class of logic devices that can be easily configured to perform a desired logic operation. Field programmable gate arrays (FPGA) are a typical example. These devices may be programmed many times to perform different logic operations. Most importantly, they can be programmed to create gate array prototypes instantaneously, allowing complete dynamic reconfigurability.
System designers commonly use reconfigurable logic devices such as FPGAs to test digital logic designs prior to manufacture or fabrication for hardware debugging or to expose other design flaws. Usually, these tests are termed emulations in which a reconfigurable logic system constructed from the devices models the logic design, such as a microprocessor, in order to confirm the proper operation of the logic design along with possibly its compatibility with an environment or user system in which it is intended to operate. In the tests, a netlist describing the internal architecture of the logic design is compiled for a specific class of reconfigurable devices and then loaded by some type of configuring system, such as a host workstation, into a reconfigurable system constructed from the class of devices. If the reconfigurable logic system is a single or array of FPGAs, the loading step is as easy as down-loading a file describing the compiled netlist to the FPGAs. The programmed configurable logic system is then tested in the user environment by confirming that its response to user data signals and user clock signals agrees with the design specifications for the design.
Recently, most of the attention in complex logic design modeling has been directed to reconfigurable systems built from heterogeneous networks of special purpose FPGA processors connected to exchange signals via some type of interconnect. The networks are heterogeneous not necessarily in the sense that they are composed of arrays of different devices but that the devices have been individually configured to cooperatively execute different sections, or partitions, of the overall user logic design. These networks rely on static routing at compile-time to organize the propagation of logic signals through the FPGA network. Static refers to the fact that all data or logic signal movement can be determined and optimized during compiling.
Logic analysis techniques are often applied to these FPGA networks. Typically, the networks are constructed for the intended purpose of identifying flaws in the user design. Other times, however, a flaw may exist at the level of the FPGA network. That is, the logic design may not be the source of the problem but, in the process of adapting the user logic design to the FPGA network, some improper operation such as hold time errors arose. Logic analysis is a process by which digital logic values of logic signals propagating within the FPGA processor are sampled and compared with the values those logic signals should have if the system were operating properly. When improper operation is discovered according to this process, faults in the original user logic design or at the level of the compiled netlist can be corrected by reconfiguration and reloading a new compiled netlist.
A logic analyzer is commonly used to perform the logic analysis. These devices have a number of channels with corresponding probes that are physically connected to the conductors in the FPGA network on which the logic signals of interest propagate. The logic analyzer is then provided with some trigger condition. Usually, a trigger condition is at least in part defined by the user clock signal, i.e., the clock signal from the user environment defining the operation cycles of the FPGA network. The trigger condition is also usually established by other logic signals from the FPGA network. For example, if it is known that a particular logic design is not operating properly during data writes to a bus, then the trigger condition might be enabled in part in response to a write enable signal within the logic design. At occurrence of the trigger condition, the analyzer samples the logic signals.
Other logic analysis tools are known for FPGA networks. Since the FPGA networks are completely configurable and additional processing power is added by providing additional FPGAs, some have implemented a logic analyzer in the FPGA network alongside the portion of the network that is dedicated to emulating or modeling the user logic design. Usually, such a system takes the form of a circular or FIFO, first-in-first-out, buffer. Logic values from the logic signals of interest are written to the buffer until a trigger condition is met. At this point, the contents of the buffer are frozen. A host workstation can then be used to read out the contents of the buffer for analysis to determine the origin of any faults or confirm the proper operation.
SUMMARY OF THE INVENTION
One of the most significant problems that arises when using commercially available logic analyzers on FPGA networks is the fact that there is a fundamental difference in the type of analysis that the logic analyzers are designed to perform and the type of analysis that is required when surveying the FPGA network. Commercially available logic analyzers provide the functionality required by the largest segments of the commercial markets for these devices. And, most applications for the devices involve the logic analysis of conventional logic circuits that have a single microprocessor chip, memory, and peripheral devices, for example. Such systems operate relatively quickly, such as a hundred megahertz, and have only few logic signals available for sampling since most signals are hidden within the chips. The chips perform comparatively complex logic operations and logic signals are only available at the boundaries of these chips. The commercial analyzers are not designed for the logic analysis of FPGA processing networks comprising a large number of FPGA chips, each having a relatively low level of integration in the sense of the number or complexity of logic operations that each chip can perform. Here, a much larger range of signals are available since signals that would usually be entirely within a microprocessor, for example, are now exposed and available to be sampled by the logic analyzer. Further, the FPGA processors operate at slowed user clock speeds of, for example, one or two MHz. In short, commercially available logic analyzers are designed to sample relatively few signals, but sample these signals at a very high clock rate. In contrast, the logic analysis of FPGA networks does not require fast signal sampling since the user clock is typically slow. A much wider range of logic signals, however, are available and would desirably be sampled in order to provide a generous spectrum of signals from which to assess the operation of the network.
The present invention overcomes the above-identified problems while still relying on the commercially available logic analyzers. As a result, the complex logic analysis tools need not be programmed into the logic design as provided in some approaches nor provided as dedicated logic analysis circuitry, as in others. This adds convenience in the easy operation of commercially available logic analyzers and their programmable trigger conditions. The number of signals that the logic analyzer can effectively sample is increased by configuring the FPGA system or other programmable device network to time-division multiplex logic values of the desired logic signals to the logic analyzer for cycles of the user or emulation clock signal. Therefore, in contrast to the past where only a single probe of the logic analyzer could be used to sample a single signal during a cycle of the user clock, that probe can now sample as many logic signals as can be multiplexed from the FPGA network to the logic analyzer in the user clock cycle.
In specific embodiments, the multiplexing clock signal generated by the clock generator is a virtual clock signal for the logic emulation system.
In other embodiments

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