Logic analysis subsystem in a time-sliced emulator

Details Logic analysis subsystem in a time-sliced emulator Logic analysis subsystem in a time-sliced emulator

1997-03-31

2000-10-31

Teska, Kevin J.

Data processing: structural design, modeling, simulation, and em

Emulation

703 28, G06F 9455

Patent

active

061416363

ABSTRACT:
A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.

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