Logarithmic value calculation circuit

Details Logarithmic value calculation circuit Logarithmic value calculation circuit

1999-01-19

2002-02-05

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06345285

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a decibel value calculation circuit for computing a logarithmic value y of input data x, and more particularly to a decibel value calculation circuit for computing it by separating into mantissa value a and exponent value b on the basis of expression of data x=a·2
b
.
2. Description of the Related Art
Conventionally, audio data and image data to be stored or transmitted are encoded and compressed, and a logarithm of such data is often taken to calculate a decibel value. For example, encoding compression processing of such data generally includes processing to quantize data by allotting a predetermined number of bits to it. When the number of quantized bits is allotted, a signal level is often referred to, and it is necessary to calculate the decibel value of data.
If an input data value is x and a decibel value is y, the decibel value is calculated by logarithmic calculation as follows:
y=&agr;·log
10
x
where, &agr; is a constant such as 10 or 20.
Conventionally, software installed in a microcomputer is used to make such calculation.
However, such computational software has a disadvantage in that computation requires significant time. It is especially desirable for a device such as an MD (mini disc) player to have a data-processing circuit integrated into a single integrated circuit. It is desirable that the entire circuit be formed of a simple circuit and be able to calculate at a satisfactorily high speed. Therefore, it is desired that the circuit for calculation be made of hardware and have a simple configuration.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a decoder which can make the above-described computation by a relatively simple small-scale circuit.
The invention processes input data x by separating it into mantissa value a and exponent value b by a separator. Thus, ROM is only used to store a table of log
10
a, and its size can therefore be very small. Exponent value b is multiplied with a constant n·log
10
2 (n=integer) by a multiplier. Addition of output from the ROM and that from the multiplier by an adder can result in a calculated result y. Accordingly, a small table and single multiplication and addition are all required to be made, so that the circuit can be made simple, and high-speed arithmetic can be performed.
According to a preferred embodiment of the invention, the separator converts the data x expressed with a fixed point into data expressed with a floating point.


REFERENCES:
patent: 5363321 (1994-11-01), Trong et al.
patent: 5600581 (1997-02-01), Dworkin et al.
patent: 5629884 (1997-05-01), Pan
patent: 5642305 (1997-06-01), Pan
patent: 5933360 (1999-08-01), Larson
patent: 5951629 (1999-09-01), Wertheim et al.

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