Logarithmic linear variable gain CMOS amplifier

Details Logarithmic linear variable gain CMOS amplifier Logarithmic linear variable gain CMOS amplifier

2004-09-01

2010-06-15

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Logarithmic

C327S063000, C330S254000

Reexamination Certificate

active

07737759

ABSTRACT:
A logarithmic linear variable gain CMOS amplifier includes first and second differential pairs of transistors forming a differential input, with each differential pair of transistors including a common source node. A pair of diode-connected load transistors is connected to the first and second differential pairs of transistors, and a third differential pair of transistors is connected to the pair of diode-connected load transistors. The third differential pair of transistors include respective gates connected together and in parallel to gates of the first and second differential pairs of transistors. First and second current mirrors are respectively connected to the common source nodes of the first and second differential pairs of transistors for programmably injecting respective bias currents thereto, with a sum of the respective bias currents remaining constant.

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William H. Hayt, Jr. & Jack E. Kemmerly, Engineering Circuit Analysis 34 (3rd ed. 1978).
Stan Gibilisco, The Illustrated Dictionary of Electronics 477 (8th ed. 2001).

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