Logarithmic amplifying circuit based on the bias-offset techniqu

Details Logarithmic amplifying circuit based on the bias-offset techniqu Logarithmic amplifying circuit based on the bias-offset techniqu

1994-07-13

1996-04-09

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Logarithmic

327352, 327307, G06F 7556, G06G 724

Patent

active

055065376

ABSTRACT:
A logarithmic amplifying circuit with a reduced power dissipation and suitable for applying to an integrated circuit. The logarithmic amplifying circuit has cascade-connected differential amplifiers, a rectifier connected to each if the amplifiers and an adder for adding the output currents of the rectifiers. Each of the rectifiers has a differential pair composed of a plurality of transistors emitter-coupled or source-coupled, a constant current source for a tail current of the differential pair and an offset voltage source for superimposing a DC offset voltage on a differential input voltage to be supplied to the differential pair.

REFERENCES:
patent: 4794342 (1988-12-01), Kimura
patent: 4990803 (1991-02-01), Gilbert
patent: 5057717 (1991-10-01), Kimura
patent: 5345185 (1994-09-01), Gilbert
K. Kimura, "Some Circuit Design Techniques for . . . on low Supply Voltage", IEEE Transactions on Circuits and Systems--I: Fundamental Theory and Applications, vol. 39, No. 9, Sep. 1992, pp. 771-777.
K. Kimura, "A Unified Analysis of Four-Quadrant . . . Transistors Operable on Low Supply Voltage", IEICE Trans. Electron., vol. E76-C, No. 5, May 1993, pp. 714-737.

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