Logarithmic amplifier circuit

Details Logarithmic amplifier circuit Logarithmic amplifier circuit

1991-01-30

1991-10-15

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328145, G06F 7556, G06F 724

Patent

active

050577174

ABSTRACT:
A logarithmic amplifier circuit has n (n>1) stages of differential amplifiers, n+1 in number, of rectifying circuits, a differential pair of bipolar transistors having different emitter sizes in the ratio of 1/J (J>1) and a differential pair of MOS transistors of which the ratio of a gate-width and a gate-length W/L is 1/K (K>1). The bipolar transistors and the MOS transistors form an output pair. A collector of one of the bipolar transistors having a larger emitter size and a drain of one of MOS transistors having a larger W/L ratio are connected together, and a collector of the other of bipolar transistors having a smaller emitter size and a drain of the other of MOS transistors having a smaller W/L ratio are connected together. A subtraction circuit outputs a difference in the currents flowing in each of the output pair and outputs from all the subtraction circuits are added up at a common load resistor. The arrangement enables the realization of a highly accurate logarithmic amplifier circuit which operates at a low power supply voltage and has a wide dynamic range.

REFERENCES:
patent: 4442549 (1984-04-01), Main
patent: 4680553 (1987-07-01), Kimura et al.
patent: 4972512 (1990-11-01), Garskamp
patent: 4990803 (1991-02-01), Gilbert

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