Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Logarithmic
Reexamination Certificate
2002-05-24
2004-05-11
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
Logarithmic
C327S351000, C327S352000
Reexamination Certificate
active
06734712
ABSTRACT:
BACKGROUND OF THE INVENTION
A logarithmic amplifier is a device that provides an output signal that will increment by a fixed amount each time the input signal increases by some factor. For example, a log amplifier may be designed to increment its output signal in response to a tripling or quadrupling of the input signal.
Early developments in logarithmic amplifiers came from the need to create a form of automatic gain control with high dynamic range in receivers for radar and electronic warfare. In these applications, the received signal power can vary by many orders of magnitude due to obstructions and reflections in the transmitting path. Logarithmic amplifiers are used to compress this large signal range into a smaller range that is more easily monitored on an electronic display or more easily captured with an analog-to-digital converter. Furthermore, a log amplifier may be used wherever the need for logarithmic arithmetic arises in instrumentation and signal processing in general.
Logarithmic amplifiers may also be used in fiber-optic receivers for gain control. The detected power in a fiber-optic receiver can vary due to bias point drift in both the transmitting laser and the receiver photodiode. Logarithmic amplifiers have been used to compress the high range of power levels provided by the photodiode. The advantage is to ease the task of the decision circuitry within the receiver and to protect it from optical overload.
Logarithmic converters may also be used in optical transmitters to aid in the task of performing single-sideband modulation of optical signals. An optical modulation system
10
that uses a logarithmic converter is shown in FIG.
1
. An electrical information signal
100
is input to an optical amplitude modulator
104
, and so the information signal amplitude-modulates the optical signal
102
. As well, the signal is input to a logarithmic converter
106
serially coupled to a Hilbert transformer
108
. Using an optical phase modulator
110
, the output of the Hilbert transformer is used to phase-modulate the output of the optical amplitude modulator. The output of the phase modulator is an optical single-sideband signal
112
. This scheme is particularly suited to high-data rate, baseband digital signals. The modulator is further described in U.S. Pat. No. 5,949,926.
There are two general categories of logarithmic converters; single stage converters and piecewise-approximate converters. Single stage converters, such as those that exploit the exponential voltage-to-current relation of PN junctions in bipolar transistors and diodes, provide efficient logarithmic conversion in low frequency applications. However, the present invention is concerned with high frequency operation and so only converters providing a piecewise-approximation to a logarithm are considered.
Piecewise-approximate logarithmic amplifiers may be subdivided into those that operate in a ‘true’ mode (also called ‘baseband’ or ‘video’), or a demodulating mode, or those that may operate in both modes. Demodulating logarithmic amplifiers provide the logarithm of the envelope of the input signal, as opposed to the logarithm of the entire signal provided by true logarithmic amplifiers. The present invention is primarily concerned with improving logarithmic amplifiers operating in the true mode, and so the demodulating ability of logarithmic amplifiers will not be discussed further here.
A progressive-compression logarithmic amplifier
20
is shown in FIG.
2
. The signal path includes serially coupled amplifiers
204
, with the output voltage of each amplifier coupled to a limiting transconductance element
206
. The unamplified input signal is coupled to limiting transconductance element
206
A that has a higher gain than elements
206
.
FIG. 3
parts (a) and (b) show the input-output characteristic of transconductance elements
206
and
206
A respectively. A current bus
208
sums the output currents of all such elements to provide a system output current that is logarithmically related to the input signal
202
. Typically the current bus is terminated by a resistive element
210
to provide an output voltage
212
. Since the currents are summed in parallel, amplifier
20
belongs to the class of parallel summation logarithmic amplifiers.
In the progressive-compression amplifier in
FIG. 2
, relatively small input signals are simply amplified, whereas larger signals will cause the transconductance elements in each path to limit, starting with the last path and progressing toward the first path.
FIG. 4
shows the DC response
402
of amplifier
20
, where the transfer function of a four-path progressive-compression amplifier is shown. The amplifier response approximates a straight line in
FIG. 4
because it is plotted on a semi-logarithmic axis. In order to reduce the error between the cusps of the approximation, more stages with smaller gains must be cascaded.
Progressive-compression amplifiers take advantage of multiple cascaded amplifiers to provide high gain. High gain directly translates into high dynamic range, because the logarithmic dynamic range extends from the point where the gain is highest to where the gain compresses to zero. In addition, progressive-compression amplifiers are easy to design since all of the cascaded stages are the same or similar. They also exhibit high tolerance to manufacturing process and temperature variations since these factors are likely to effect the gain of amplifiers
204
equally, which will simply shift or scale the logarithmic response without significantly distorting its logarithmic characteristics.
A limit on the frequency range of the progressive-compression amplifier may be seen by considering that the component amplifiers
204
each have finite bandwidth. If a single pole dominates the frequency response of these amplifiers, then the phase response of each amplifier will be close to −45 degrees near the pole frequency. The input signal
202
in
FIG. 2
will pass through element
206
A to the current bus with little phase shift, and this signal must be added in parallel with the output of the last serially-coupled amplifier
204
which will have significant phase shift from having passed through several amplifiers. Hence, if out-of-phase addition is to be avoided, either the amplifier must be operated well below its frequency limit, or the signals with little phase delay must have phase delay added to them prior to summation.
Another type of serially coupled logarithmic converter that exhibits better internal phase matching is the series linear-limit logarithmic amplifier
50
shown in
FIG. 5
, also known as the twin-gain stage logarithmic amplifier from A. Woroncow and J. Croney, “A True I.F. Logarithmic Amplifier using Twin-Gain Stages”, The Radio and Electronic Engineer, September 1966, pp. 149-155. A number of identical stages
508
consisting of a limiting amplifier
506
in parallel with a buffering network
502
are cascaded. An input signal
504
that is relatively small will simply be amplified by all stages, while larger signals will cause the limiting amplifiers
506
to limit, starting with the last stage and progressing toward the input. The DC transfer function
404
of a logarithmic amplifier with three twin-gain stages is shown in FIG.
4
. It may be seen that the response of the twin-gain stage amplifier is similar to that of the progressive-compression amplifier except beyond point
406
. Point
406
approximately indicates the highest power levels handled by the logarithmic amplifier. Correct operation of the twin-gain stage amplifier requires that all of the buffering amplifiers
502
continue to pass the signal up to the input voltage indicated by point
406
. The effect of this requirement on the bandwidth of the twin-gain stage
508
may be shown using the schematic diagram of one of the twin-gain stages in FIG.
6
.
FIG. 6
shows two parallel differential-pair amplifiers in bipolar integrated circuit technology with shared collector resistance
602
. The high-gain limiting amplifier includes transistors
6
Davies Robert J.
Haslett James W.
Holdenried Christopher D.
McRory John G.
Christensen O'Connor Johnson & Kindness
Lam Tuan T.
Nguyen Hiep
Telecommunications Research Laboratories
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