Log converter utilizing offset and method of use thereof

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

708277, 341 75, G06F 700, G06F 1500

Patent

active

060650311

ABSTRACT:
A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).

REFERENCES:
patent: 4626825 (1986-12-01), Burleson et al.
patent: 4682152 (1987-07-01), Okamoto et al.
patent: 5184317 (1993-02-01), Pickett
patent: 5343254 (1994-08-01), Wada et al.
patent: 5359551 (1994-10-01), Pickett
"The Efficient Implementation and Analysis of a Hybrid Number System Processor" by Fangshi Lai, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 40, No. 6, Jun. 1993.
A Logarithmic Vector Processor for Neural Net Applications by Steve Richfield, Neurosoft, IEEE First Int'l Conference on Neural Networks, Sheraton Harbor Island East, San Diego, CA, Jun. 21-24, 1987.
A Multiplier-Less Digital Neural Network by L. Spaaneburg, B. Hoefflinger, S. Neusser, J.A.G. Nijhuis, A. Siggelkow, IMS, Stuttgart, Germany, Proceedings of the 2nd Int'l Conference on Microelectronics for Neural Networks, Oct. 16-18, 1991, Munich, F.R. Germany.
Algorithm Design for a 30 bit Integrated Logarithmic Processor by David M. Lewis and Lawrence K. Yu, Dept. of Elec. Engr., Univ. of Toronto, Proceeding 9th Symposium on Computer Arithmetic, 1989, IEEE Comp. Soc. Press, Press, pp. 192-199.
A 30-b Integrated Logarithmic Number System Processor by Lawrence K. Yu, Member, IEEE, and and David M. Lewis, Member, IEEE, IEEE Journal of Solid-State Circuits, vol. 26, No. 10, Oct. 1991, pp. 1433-1440.
An Accurate LNS Arithmetic Unit Using Interleaved Memory Function Interpolator by David M. Lewis, Dept. of Elec, Engr., Univ. of Toronto, Proceeding 11th Symposium on Computer Arithmetic, 1993, IEEE Comp.. Soc. Press, pp. 2-9.
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit by David M. Lewis, Member, IEEE, IEEE Transactions on Computers, vol. 43, No. 8, Aug. 1994, pp. 974-982.
Table-Lookup Algorithms for Elementary Functions and Their Error Analysis by Ping Tak Peter Tang, Mathematics and Computer Science Div., Argonne Nat'l Laboratory, 9700 S. Cass Ave., Argonne, IL 60439-4801, Proceeding 10th Symposium on Computer Arithmetic, Jun. 1991, pp. 232-236.
Applying Features of IEEE 754 to Sign/Logarithm Arithmetic by Mark G. Arnold, Member, IEEE, T. A. Bailey, Member, IEEE, J. R. COwles, and M. D. Winkel, IEEE Transactions on Computers, vol. 41, No. 8, Aug. 1992, pp. 1040-1050.
D8.13 Improved Accuracy for Logarithmic Addition in DSP Applns. by Mark G. Arnold, J. Cowles, and T. Bailey, Computer Science Dept., Univ. of Wyoming, Laramie, WY, ICASSP 88: Int. Conf. on Acoustics, Speech and Signal Processing, vol. 3, pp. 1714-1717.
Redundant Logarithmic Number Systems by M.G. Arnold, T.A. Bailey, J.R. Cowles, J.J. Cupal, Univ. of Wyoming, Laramie, WY, Proceeding of 9th Symposium on Computer Arithmetic, pp. 144-151, IEEE Comp. Soc. Press.
Comments on "An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System" by M. Arnold, T. Bailey, and J. Cowles, IEEE Transactions on Computers, vol. 41, No. 6, Jun. 1992, pp. 786-788.
Redundant Logarithmic Arithmetic, M. G. Arnold, Member IEEE, T. A. Bailey, Member IEEE, J.R. Cowles, and J.J. Cupal, Members IEEE, IEEE Transactions on Computers, vol. 39, No. 8, Aug. 1990, pp. 1077-1086.
A 10-ns Hybrid Number System Data Execution Unit for Digital Signal Processing Systems, Fang-shi Lai, Member IEEE, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.
A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities, Fang-shi Lai, Memeber IEEE, Ching-Farn Eric Wu, Member IEEE, IEEE Transactions on Computers, vol. 40, No. 8, Aug. 1991.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Log converter utilizing offset and method of use thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Log converter utilizing offset and method of use thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Log converter utilizing offset and method of use thereof will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-268292

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.