Log-conformance error correction circuit for semiconductor devic

Details Log-conformance error correction circuit for semiconductor devic Log-conformance error correction circuit for semiconductor devic

1981-05-18

1984-03-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307491, 328145, G06G 712

Patent

active

044356552

ABSTRACT:
A log-conformance correction circuit for a prototype circuit employing semiconductor devices comprises a quad of devices with voltage drops arranged in series, and currents or current densities driven such that the logarithmic components in the voltage drops sum to zero while log-conformance error components are produced. A correction quad suitably may comprise two pairs of semiconductor devices in which the current densities in one pair are cross-proportional with the current densities of the other pair, and of a different magnitude to establish a current density ratio between the pairs. The log-conformance error components which are generated by the correction quad are inserted into the prototype circuit to cancel log-conformance error therefrom.

REFERENCES:
patent: 4038566 (1977-07-01), Evans
patent: 4156283 (1979-05-01), Gilbert
patent: 4157512 (1979-06-01), Schnioock
patent: 4308471 (1981-12-01), Misawa
patent: 4353000 (1982-10-01), Noda

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