LOCOS on SOI and HOT semiconductor device and method for...

Details LOCOS on SOI and HOT semiconductor device and method for... LOCOS on SOI and HOT semiconductor device and method for...

2008-07-22

2008-07-22

Sefer, A. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S351000, C257S510000, C257S547000, C257SE21545, C257SE21540

Reexamination Certificate

active

07402885

ABSTRACT:
One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of LOCOS regions may be formed on opposite sides of a PFET gate and its corresponding channel, or one or more LOCOS regions may more fully surround, or even completely surround, the PFET channel. In addition, one or more slits may be formed in the LOCOS regions as appropriate to reduce or even completely neutralize the compressive strain in certain directions that would otherwise be applied without the slits. These techniques may be used in silicon-on-insulator (SOI) wafers with or without hybrid orientation technology (HOT) regions.

REFERENCES:
patent: 5841170 (1998-11-01), Adan et al.
patent: 6462379 (2002-10-01), Higashi et al.
patent: 6602613 (2003-08-01), Fitzgerald

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