Locking display pixel clock to input frame rate

Details Locking display pixel clock to input frame rate Locking display pixel clock to input frame rate

2007-08-07

2007-08-07

Kostak, Victor R. (Department: 2622)

Television

Synchronization

Automatic phase or frequency control

C348S547000, C348S194000, C327S119000, C327S159000

Reexamination Certificate

active

11182102

ABSTRACT:
To match the output frame rates to the input frame rates, a display clock signal is generated that has a frequency locked to the frequency of a reference clock signal. To generate the display clock signal, the period of the vertical incoming data clock is measured using the reference clock signal. The number of pixels disposed in the output frames is subsequently divided by the measured period. A fractional-N phase-locked loop circuit is adapted to multiply the result of the division with the frequency of the reference clock signal to generate the display clock signal. The display clock signal is also locked to the reference clock signal.

REFERENCES:
patent: 5719510 (1998-02-01), Weidner
patent: 6208183 (2001-03-01), Li et al.
patent: 6987424 (2006-01-01), Hein
patent: 2005/0013343 (2005-01-01), Giunco et al.

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