Locked loop with dual rail regulation

Details Locked loop with dual rail regulation Locked loop with dual rail regulation

2005-06-28

2005-06-28

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06911853

ABSTRACT:
An apparatus having a dual rail regulated reference loop. The reference loop includes a delay circuit powered by upper and lower supply voltages to generate a plurality of reference clock signals, and a voltage regulation circuit to adjust the upper and lower supply voltages according to a phase difference between a selected pair of the reference clock signals.

REFERENCES:
patent: 5206881 (1993-04-01), Messenger et al.
patent: 5554945 (1996-09-01), Lee et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5635995 (1997-06-01), Strolle et al.
patent: 5684421 (1997-11-01), Chapman et al.
patent: 5731727 (1998-03-01), Iwamoto et al.
patent: 5742798 (1998-04-01), Goldrian
patent: 5852378 (1998-12-01), Keeth
patent: 5880612 (1999-03-01), Kim
patent: 5883533 (1999-03-01), Matsuda et al.
patent: 5889423 (1999-03-01), Trumpp
patent: 5892981 (1999-04-01), Wiggers
patent: 5920518 (1999-07-01), Harrison et al.
patent: 5940608 (1999-08-01), Manning
patent: 5940609 (1999-08-01), Harrison
patent: 5945862 (1999-08-01), Donnelly et al.
patent: 5946244 (1999-08-01), Manning
patent: 5963502 (1999-10-01), Watanabe
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6016282 (2000-01-01), Keeth
patent: 6026050 (2000-02-01), Baker et al.
patent: 6026051 (2000-02-01), Keeth et al.
patent: 6029250 (2000-02-01), Keeth
patent: 6029252 (2000-02-01), Manning
patent: 6031788 (2000-02-01), Bando et al.
patent: 6043717 (2000-03-01), Kurd
patent: 6047346 (2000-04-01), Lau et al.
patent: 6085284 (2000-07-01), Farmwald et al.
patent: 6101197 (2000-08-01), Keeth et al.
patent: 6101612 (2000-08-01), Jeddeloh
patent: 6104228 (2000-08-01), Lakshmikumar
patent: 6108795 (2000-08-01), Jeddeloh
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6133773 (2000-10-01), Garlepp et al.
patent: 6198356 (2001-03-01), Visocchi et al.
patent: 6255912 (2001-07-01), Laub et al.
patent: 6304116 (2001-10-01), Yoon et al.
patent: 6321282 (2001-11-01), Horowitz et al.
patent: 6373308 (2002-04-01), Nguyen
patent: 6437619 (2002-08-01), Okuda et al.
patent: 6469555 (2002-10-01), Lau et al.
patent: 6470060 (2002-10-01), Harrison
patent: 6483360 (2002-11-01), Nakamura
patent: 6504438 (2003-01-01), Chang et al.
patent: 6580305 (2003-06-01), Liu et al.
patent: 6759881 (2004-07-01), Kizer et al.
patent: 6784714 (2004-08-01), Nakamura
patent: 2001/0053187 (2001-12-01), Simon et al.
patent: 2002/0084867 (2002-07-01), Kim
patent: 2002/0140472 (2002-10-01), Sonobe
patent: 02000035831 (2000-02-01), None
patent: WO 01/29680 (2001-04-01), None
patent: WO 02/11355 (2002-02-01), None
John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Gu-Yeon Wei et al., “A Variable-Frequency Parallel I/O Interface with Adaptive Power-Supply Regulation,” IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1600-1609.
Stefanos Sidiropoulos et al., “Circuit Design for a 2.2GB/s Memory Interface,” 2001 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 70-71.
Bang-Sup Song and David C. Soo, “NRZ Timing Recovery Technique for Band-Limited Channels,” IEEE Journal of Solid-State Circuits, vol. 32, No. 4, Apr. 1997, pp. 514-520.
John Poulton, “Signaling in High-Performance Memory Systems,” ISSCC, 1999, pp. 1-59.

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