Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2007-07-03
2007-07-03
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S157000
Reexamination Certificate
active
11264111
ABSTRACT:
Clock generators include phase-locked and delay-locked loop integrated circuits that support efficient high speed testing of clock frequencies. An integrated circuit device is provided with a clock signal generator having at least one delay element therein that is responsive to a control signal. A speed tracking circuit is also provided. This speed tracking circuit is configured to generate a signal having a measurable characteristic that tracks changes in a property of the control signal that influences a delay of the at least one delay element.
REFERENCES:
patent: 5629650 (1997-05-01), Gersbach et al.
patent: 5686864 (1997-11-01), Martin et al.
patent: 5727037 (1998-03-01), Maneatis
patent: 5942949 (1999-08-01), Wilson et al.
patent: 5982836 (1999-11-01), Sakae et al.
patent: 6031427 (2000-02-01), Black
patent: 6043695 (2000-03-01), O'Sullivan
patent: 6275115 (2001-08-01), Egawa
patent: 6329882 (2001-12-01), Fayneh et al.
patent: 6411144 (2002-06-01), Matsuno
patent: 6661267 (2003-12-01), Walker et al.
patent: 6744293 (2004-06-01), Fu et al.
patent: 6784707 (2004-08-01), Kim et al.
patent: 6867627 (2005-03-01), Murtagh
patent: 6894569 (2005-05-01), Fayneh et al.
patent: 6903586 (2005-06-01), Abbasi et al.
patent: 6952124 (2005-10-01), Pham
patent: 6963234 (2005-11-01), Bidenbach
patent: 6987409 (2006-01-01), Kim et al.
patent: 7061332 (2006-06-01), Siniscalchi et al.
patent: 7109764 (2006-09-01), Sakamoto et al.
Maneatis, John G., “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996.
Mansuri et al., “A Low-Power Adaptive Bandwidth PLL and Clock Buffer with Supply-Noise Compensation,” IEEE Journal of Solid-State Circuits, vol. 38, No. 11, Nov. 2003.
Sidiropoulos, et al., “SA 20.2: A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range,” Center for Integrated Systems, Stanford University, Stanford, CA, Admitted Prior Art, no date.
Maneatis, John G., “FA8.1 Low-Jitter and Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 130-132, no date.
Maneatis, John G., Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, High Speed CMOS IC Lab, Postech, Dec. 24, 2004, http://aslc.postech.ac.kr/3.Class/1.Classes/04—695v/1224bjh.pdf.
Fang Al Xuefeng
Xu Chao
Hernandez William
Integrated Device Technology Inc.
Lam Tuan T.
Myers Bigel & Sibley Sajovec, PA
LandOfFree
Locked-loop integrated circuits having speed tracking... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Locked-loop integrated circuits having speed tracking..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Locked-loop integrated circuits having speed tracking... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3755917