Lock warning mechanism for a cache

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G06F 1300

Patent

active

050290720

ABSTRACT:
In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed using translation tables in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in the translation tables in association with the translation descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.

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