Lock/unlock indicator for PLL circuits

Details Lock/unlock indicator for PLL circuits Lock/unlock indicator for PLL circuits

1998-01-22

1999-05-18

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 11, 331 25, 331DIG2, 327159, H03L7/095

Patent

active

059054107

ABSTRACT:
A lock circuit for indicating a locked/unlocked condition of phased lock loops circuits, which uses a reference clock signal input to a good-cycle counter and to a bad-cycle counter to signal a set/reset latch to output a signal indicating whether or not the phase of the output signal and input clock are in phase. Phase detector inputs are XOR gated to produce a pulse when the phase locked output clock is in a bad cycle indicated by the phase locked output clock not being in-phase with its input clock. Pulses on the XOR gate output on a bad cycle feed a single cycle counter reset circuit. The single cycle counter reset circuit on every cycle resets one of the bad and good counters based on its detection of a bad cycle pulse from the XOR gate. The good-cycle counter's output is to the SET input of the set/reset latch, and the bad-cycle counter's output is to the RESET input of the set/reset latch . We enable specific cycling of both the good and bad counters.

REFERENCES:
patent: 4617520 (1986-10-01), Levine
patent: 5680076 (1997-10-01), Kelkar et al.
patent: 5734273 (1998-03-01), Mudd

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