Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Reexamination Certificate
2000-06-27
2003-04-15
Kincaid, Kristine (Department: 2173)
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
C382S149000
Reexamination Certificate
active
06549222
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the analysis of semiconductor integrated circuits and, in particular, to a man-machine interface for manipulating a plurality of images representative of a surface of a deconstructed semiconductor integrated circuit (IC) to extract design and layout information therefrom.
BACKGROUND OF THE INVENTION
In the semiconductor industry it is often necessary to physically analyze semiconductor integrated circuits (ICs) for the purposes of product reliability assurance, design validation and identification of device structural patterns. ICs are analyzed to extract design and/or layout information therefrom. This process is known as reverse-engineering. Reverse-engineering is also part of the test and development process in the manufacture of ICs on a large scale. In general, a vast amount of time and manual labor is required to reverse-engineer an IC.
An IC is a monocrystaline silicon die upon which a large number of transistors and other electronic components have been fabricated and interconnected to form a useful circuit. During manufacture, each die is part of a larger silicon wafer substrate which facilitates handling and simultaneous processing of a plurality of ICs.
The IC fabrication process includes: doping the silicon substrate to change its conductive properties and building up a sequence of layers onto the silicon substrate using different techniques. Doping layers are created using ion implantation. Diffusion layers are created by depositing dopants on top of a substrate and heating the wafer. With each deposition layer, different materials are deposited and selectively removed by selective etching in accordance with a predetermined pattern. Components manufactured on the silicon wafer span multiple layers. Oxide layers are used for insulation. Deposited metal layers are used to interconnect individual terminals of the components so formed.
It is the identification of these components and the interconnections provided by the metal layers that provides base information from which the design and/or layout of an IC can be extracted and verified.
In reverse-engineering a sample IC, the die is deconstructed. The IC sample die is subjected to a progressive layer-removal sequence utilizing an exacting series treatment, such as acid etchants, each of which is specifically chosen to remove a single layer at the time. Other deconstructive treatments include dry etching, polishing, etc. Using such treatments, interconnecting metal layers, polycrystalline silicon layers, oxide layers, etc. are removed step-by-step. At each deconstructive step the surface of the partly deconstructed IC is inspected.
Inspection techniques include the use of: optical microscopes, scanning electron microscopes, and other surface inspection equipment. In general, the scanning electron microscope is accurate but is expensive to own and operate. Optical microscopes can be used in brightfield, contrast interference and darkfield modes of illumination.
In the brightfield or contrast interference modes, the physical extents of the components on the die are distorted by fringe effects. These fringe effects can be interpreted by an experienced human analyst but require vast amounts of computation for analysis by a computer.
A “METHOD OF EXAMINING MICROCIRCUIT PATTERNS” is described in the U.S. Pat. No. 4,623,255 which issued Nov. 18, 1986 to Suszko. The method involves photographing an IC die in between deconstructive steps. Film transparencies are printed and used by an engineer analyst to extract design and layout information from the photographed IC. While the teachings of Suszko have merit, design and layout extraction are impeded by the handling and cross-correlation of the bulky transparencies.
Another “AUTOMATED SYSTEM FOR EXTRACTING DESIGN AND LAYOUT INFORMATION FROM AN INTEGRATED CIRCUIT” is described by Yu et al. in U.S. Pat. No. 5,086,477 which issued Feb. 4, 1992. A digital camera and a controlled stage are used to capture images in overlapping tile fashion after each deconstructive step. The captured digital images are stored in a computer memory and reassembled into image-mosaics based on the overlap at the borders of each tile image. Yu et al. describe pattern matching performed on an image-mosaic of a deconstructive step, and points out the difficulties involved in extracting layout information from the tile images. The automated system to Yu et al. appears to be suitable for extracting design information from complex ICs that are difficult to reverse engineer. To accomplish this, “cell” libraries are built. The cell libraries contain images of specific arrangements of components that are known to perform a specific function.
The cell libraries are used for automated pattern matching in order to facilitate reverse engineering of Application Specific Integrated Circuits (ASICs), for example. However, Yu et al. fail to describe how multiple image-mosaics, each representing a different step in the deconstruction of an IC, are manipulated in order to extract design and layout information concurrently therefrom. Concurrent analysis of image-mosaics is desirable because individual components fabricated on the silicon wafer may span multiple layers.
There is therefore a need for a man-machine interface that enables manipulation of multiple images of an IC to facilitate concurrent extraction of design and layout information therefrom.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a man-machine interface adapted to facilitate feature recognition and analysis across multiple images representative of one or more surfaces of a semiconductor integrated circuit (IC).
It is another object of the invention to provide a man-machine interface that supports multiple views, each view displaying a portion of an image-mosaic and one of a group of multiple lock-step cursors.
In accordance with one aspect of the invention a man-machine interface for analyzing image-mosaics is presented. The man-machine interface includes a display area, a system pointer, a plurality of mosaic-views and a corresponding plurality of lock-step cursors. The image-mosaics are aligned to a sample coordinate space. The display area defines a display coordinate space and the system pointer has a position with respect to the display coordinate space. Each one of the plurality of mosaic-views has view-boundaries in the display coordinate space and displays one of the plurality of image-mosaics. Each lock-step cursor has a position in the display coordinate space and shares positional coordinates in the sample coordinate space with all of the other lock-step cursors. The system pointer, when positioned within at least one view-boundary, takes on a representation of a master-cursor which controls cursor-events. Lock-step cursors are displayed in the other views at the position of the master-cursor in the sample coordinate space. The image-mosaics are, for example, representative of a deconstructed semiconductor integrated circuit (IC) sample.
According to another aspect of the invention, the man-machine interface further includes a navigation window having view-boundaries in the display coordinate space and displaying a low magnification image representative of the IC sample. The navigation window also enables the selection of at least one area-of-interest displayable in a plurality of mosaic-views.
The invention also provides a method of analyzing image-mosaics that are scaled and aligned to a sample coordinate space. The method comprises steps of displaying an area of interest of respective ones of a plurality of the image-mosaics within respective mosaic-views displayed on a display coordinate space of a man-machine interface used to analyze the image-mosaics. The method further comprises a step of tracing features of the IC across at least two of the mosaic-views using a master-cursor in a one of the mosaic-views and lock-step cursors in others of the mosaic-views. The master-cursor controls cursor events and the lock-step cursors are displayed within the other mo
(Ogilvy Renault)
Chipworks
Vu Thanh T
Wood Max R.
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