Lock sensor circuit and method for phase lock loop circuits

Details Lock sensor circuit and method for phase lock loop circuits Lock sensor circuit and method for phase lock loop circuits

1993-05-10

1994-04-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 27, 331DIG2, H03L 7089, H03L 7095

Patent

active

053049527

ABSTRACT:
A lock sensor circuit detects and indicates occurrence of a phase lock condition of an output signal of a phase lock loop (PLL) circuit when the PLL output signal is phase locked to a reference signal. A phase and frequency detector (PFD) has a reference signal input (REF IN) and a feedback signal input (VCO FBK IN) coupled to the output of the PLL circuit. The PFD delivers output UP and DOWN signals according to whether the reference signal leads or lags the feedback signal. A multi-bit up/down counter (FIG. 2 ) has UP and DOWN inputs coupled to the respective UP and DOWN outputs of the PFD and an m bit output (Q0, Q1, . . . Q10). A lock sensor circuit (50) coupled to the m bit up/down counter monitors the nth bit output (QN) of the up/down counter where n<m. A first down counter (F1, F2) counts consecutive output DOWN signals in the absence of an output UP signal. A second up counter (F3, F4) counts consecutive output UP signals in the absence of an output DOWN signal. A lock logic circuit (TLATCH, BLATCH, 64, 66, G7) is coupled through NAND gates (G1, G2) to outputs of the respective first down counter (F1, F2) and second up counter (F3,F4). The lock logic circuit generates an unlock condition indicator signal if consecutive counts of the same signal exceed a specified number and, generates a phase lock condition indicator signal at the LOCK output when no unlock condition is detected.

REFERENCES:
patent: 3982190 (1976-09-01), Schaefer
patent: 5008635 (1991-04-01), Hanke et al.

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