Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-12-27
2001-04-24
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S147000
Reexamination Certificate
active
06222400
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a lock-in detecting circuit and a method used therein and, more particularly, to a lock-in detecting circuit for a phase-locked loop incorporated in a display unit responsive to different synchronous signals such as, for example, a multiscan display unit and a method used in the lock-in detecting circuit.
DESCRIPTION OF THE RELATED ART
The display unit which selectively responds to vertical synchronous signals different in period and horizontal synchronizing signals also different in period is hereinbelow referred to as “multi-synchronization display unit”. In the multi-synchronization display unit, various kinds of signals are produced in synchronization with a horizontal synchronizing signal by controlling the deflection correcting. It is necessary for the control for the deflection correcting to synchronize the system clock with the horizontal synchronizing signal. A phase locked loop is used for the synchronization. If the system clock is out of the lock-in state, the various kinds of signals becomes uncontrollable. For this reason, the phase locked loop is associated with a lock-in detecting circuit, and the lock-in detecting circuit monitors the phase difference between the horizontal synchronizing signal and the system clock to see whether or not the phase locked loop keeps those signal in the lock-in state. The lock-in detecting circuit produces a detecting signal representative of the lock-in state or unlocked state, and the detecting signal is supplied to a controller for the deflection correcting.
FIG. 1
illustrates the relation between a phase locked loop
1
and the prior art lock-in deflecting circuit
2
. The phase locked loop
1
comprises a phase comparator
3
, a low pass filter
4
connected to the output node of the phase comparator
3
, a voltage-controlled oscillator
5
connected to the output node of the low pass filter
4
and a frequency demultiplier
6
connected between the output node of the voltage controlled oscillator
5
and one of the input node of the phase comparator
3
.
The frequency demultiplier
6
produces a low-frequency signal S
11
from a system clock signal S
44
and the low-frequency signal S
11
has a frequency regulated to 1
of the system clock S
4
. A horizontal synchronizing signal S
16
is supplied to the other input node of the phase comparator
3
, and the low-frequency signal S
11
is supplied from the frequency demultiplier
6
to the input node of the phase comparator
3
. The phase comparator
3
compares the low frequency signal S
11
with the horizontal synchronizing signal S
16
to see whether any phase difference takes place between the low frequency signal S
11
and the horizontal synchronizing signal S
16
. The phase comparator
3
produces a phase difference signal S
12
representative of the phase difference between the low-frequency signal and the horizontal synchronizing signal, and supplies the phase difference signal S
12
to the low pass filter
4
. The low pass filter
4
converts the phase difference signal S
12
to a control voltage signal, and supplies the control voltage signal to the control node of the voltage controlled oscillator
5
. The voltage controlled oscillator
5
is responsive to the control voltage signal so as to change or keep the frequency of the system clock signal S
4
.
The phase difference signal S
12
is further supplied to the prior art lock-in detecting circuit
2
. The prior art lock-in circuit
2
checks the phase difference signal S
12
to see whether the system clock S
4
and the horizontal synchronizing signal S
16
are in the lock-in state or the unlocked state. The prior art lock-in detecting circuit
2
produces a detecting signal S
20
representative of the lock-in state or the unlocked state.
FIG. 2
shows the circuit behavior of the prior art lock-in detecting circuit. A composite synchronous signal is supplied to the input node of the phase comparator
3
assigned to the horizontal synchronizing signal S
16
. While the vertical synchronous signal S
19
is maintained at a high level, the horizontal synchronizing signal S
16
is varied in frequency, and the system clock S
4
is changed to the unlocked state. Accordingly, the prior art lock-in detecting circuit
2
changes the detecting signal S
20
to the high level, and keeps the detecting signal S
20
in the high level for a certain period as indicated by arrow A
1
. This results in a malfunction.
Even though the system clock S
4
stays in the lock-in state, noise causes the phase locked loop
1
to momentarily enter the unlocked state. Even though the unlocked state continues only one clock pulse of the horizontal synchronizing signal S
16
, the prior art lock-in detecting circuit determines the phase locked loop to be in the unlocked state, and the malfunction takes place. In the worst case, the detection results in a system reset.
Plural signals are input to the multi-synchronization display unit, and the number of pulses of the horizontal synchronizing signal S
16
between the vertical synchronous pulses is not always constant. In this situation, if the detecting time period of the phase locked loop is set to a certain constant value, the phase locked loop ignores the pulses of the horizontal synchronizing signal after the detecting period, and the phase locked loop is not expected to keep the system clock signal in the lock-in state.
Other examples of the detecting circuit of the type detecting the lock-in state on the basis of the phase difference arc disclosed in Japanese Patent Publication of Unexamined Application Nos. 3-222138 and 5-327488. In detail, a phase controlling circuit is disclosed in Japanese Patent Publication of Unexamined Application No. 3-222138. The prior art phase controlling circuit firstly averages the amount of deviation between a signal to be controlled and a reference signal, and calculates the difference of the average from a standard value for the phase control. The prior art phase controlling circuit controls the phase of the signal. On the other hand, a phase synchronization circuit and a detecting circuit for detecting asynchronous state are disclosed in Japanese Patent Publication of Unexamined Application No. 5-327488. The prior art detecting circuit detects the asynchronous state through a phase comparison in the pulse width with respect to a reference clock signal.
Thus, the malfunction tends to take place in the system associated with the prior art lock-in detecting circuit, and another problem is a low discriminative capability between the asynchronous state and the other phenomena.
Although the other prior art circuits disclosed in the Japanese Patent Publication of Unexamined Applications discriminate the asynchronous state, they can not change the starting point for the detection, the detecting period and the sensitivity to appropriate values. For this reason, the prior art circuits can not establish the multi-synchronization display unit in the highly synchronous state, not exactly generate the detecting signal representative of the unlocked state.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a lock-in detecting circuit, which has a variable starting point for the detection, a variable detecting time and a variable sensitivity for producing a detecting signal exactly representing lock-in state.
It is another an important object of the present invention to provide a method for exactly detecting lock-in state.
In accordance with one aspect of the present invention, there is provided a lock-in detecting circuit associated with a phase locked loop operative to make an output signal synchronous with a first synchronizing signal, and the lock-in detecting circuit comprises a window generating means for defining a window to be opened for a first time period, a measuring means connected to the phase locked loop and the window generating means for measuring a second time period of unlocked state between the output signal and the first synchronizing signal while the window is bei
Esaki Takafumi
Fukuda Yasuhiro
Furukawa Hiroshi
Uto Yoshiyuki
McGinn & Gibb PLLC
NEC Corporation
Nguyen Linh
Tran Toan
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