Lock determination circuit of PLL for pulling up...

Details Lock determination circuit of PLL for pulling up... Lock determination circuit of PLL for pulling up...

1999-12-16

2001-12-18

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S147000

Reexamination Certificate

active

06331795

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lock determination circuit of a PLL (phase-locked loop), and in particular, a circuit for reducing power consumption of a PLL.
This application is based on patent application No. Hei 10-363576 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
FIG. 5
is a circuit diagram showing the structure of a conventional lock determination circuit of a PLL.
As shown in the figure, such a determination circuit compares two output signals, “Up” and “Down”, from a phase and frequency detector Det so as to output a signal for controlling a pull-down transistor “Tr.A”, so that the analog potential of Node
1
(see
FIG. 5
) can be changed.
In operation, the electric potential of Node
1
is gradually changed by suitably selecting the time constant determined by resistances R51 and R52 and capacitance C51.
Generally, the PLL has a function of comparing a reference clock (signal) and a comparison (i.e., feedback) clock (signal) so as to synchronize the comparison (feedback) clock with the reference clock. In addition, the PLL includes a loop filter for smoothing the detection pulse signal from the phase and frequency detector and outputting an oscillator control signal, and also includes a voltage controlled oscillator for outputting a clock signal having a predetermined frequency, by using the oscillator control signal.
In the above function the PLL, when the power supply is activated or when the reference clock is changed, a time lag is present until the lock state is realized. Therefore, in this process, it is necessary to employ a signal for monitoring the lock and unlock states, and generally, such a lock-state determining signal is controlled using an output from the phase and frequency detector.
Here, the phase and frequency detector detects the frequency/phase difference between the reference clock and comparison (feedback) clock, and outputs the detected result using the Up and Down signals.
When a frequency/phase difference exists, one of the Up and Down signals maintains the High level during a period corresponding to the difference; thus, transistor “Tr.A” is repeatedly switched to the ON state and to the OFF state in turn.
When transistor “Tr.A” is in the ON state, the electric potential of Node
1
falls with the RC time constant: R51×C51, while when transistor “Tr.A” is in the OFF state, the electric potential of Node
1
rises with the RC time constant: R52×C51.
As the lock state approaches, the High-level state of the Up/Down signal is observed sporadically and thus the Off-state period of the transistor “Tr.A” becomes longer.
When the duration of the Off state of the transistor “Tr.A” exceeds the time “R52×C51”, then the electric potential of Node
1
gradually rises. When this electric potential becomes Vdd/2, then at last the output level of the Lock terminal (see
FIG. 5
) becomes High.
After the Lock terminal becomes High and thus the lock state is determined, the electric potential of Node
1
still gradually rises towards the level Vdd, that is, Node
1
has an intermediate potential for a while.
In the above method related to
FIG. 5
, when Node
1
has such an intermediate potential before and after the lock determination timing, a current flows for a period through the gate which is driven by the intermediate potential, thereby consuming power.
SUMMARY OF THE INVENTION
In consideration of the above circumstances, an objective of the present invention is to provide a lock determination circuit of a PLL, in which the electric potential of Node
1
(the lock determination gate) can be stabilized by raising the node potential immediately after the lock determination, thereby reducing the period during which the current flows through the relevant gate and thus reducing the power consumption.
Therefore, the present invention provides a lock determination circuit of a PLL (phase-locked loop), wherein:
the PLL comprises a phase and frequency detector for comparing a reference signal and a comparison signal and outputting a detection pulse signal according to a difference between the reference and comparison signals; and
the lock determination circuit determines the lock state of an input signal to the PLL based on the detection pulse signal, and comprises:
a lock determination gate whose input level has an intermediate electric potential for a period after the lock state is determined; and
pull-up means for forcibly pulling up the input level of the lock determination gate immediately after the lock state is determined, so as to reduce a current flowing through the lock determination gate.
In the above structure, the pull-up means may include a pull-up transistor and a delay circuit, wherein:
the delay circuit is activated when the lock state is determined; and
the operation of pulling up the input level of the lock determination gate is performed by setting the pull-up transistor to the ON state for a predetermined period by using the delay circuit.
It is also possible, in the above structure, for the pull-up means to include a first delay circuit activated when the lock state is determined and a latch, and the input level of the lock determination gate is pulled up for a predetermined period by using the first delay circuit and the latch, and
the lock determination circuit further comprises:
pull-down means including a second delay circuit activated when the unlock state is determined and a latch, wherein the input level of the lock determination gate is pulled down for a predetermined period by using the second delay circuit and the latch.
According to the present invention, the electric potential of the relevant node (i.e., the input of the lock determination gate) having an intermediate potential can be raised after the lock determination to Vdd by using a pull-up transistor, latch, or the like, and can be lowered, after the unlock determination, to the ground level. Therefore, the current flowing through the lock determination gate such as an inverter (connected to the above node) can be reduced, thereby reducing the power consumption.


REFERENCES:
patent: 5256989 (1993-10-01), Parker et al.
patent: 5724007 (1998-03-01), Mar
patent: 5783956 (1998-07-01), Ooishi
patent: 5870002 (1999-02-01), Ghaderi et al.
patent: 0 484 097 (1992-05-01), None
patent: 56-86528 (1981-07-01), None
patent: 4-29411 (1992-01-01), None
patent: 7-30416 (1995-01-01), None
patent: 7-326969 (1995-12-01), None
patent: 10-98376 (1998-04-01), None
“Monolithischer CMOS-Phase-Locked-Loop-IC”. IN: Designbook 81, 1981, S. 34-36.

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