Lock detector and phase locked loop circuit

Details Lock detector and phase locked loop circuit Lock detector and phase locked loop circuit

2002-04-25

2004-03-30

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S017000

Reexamination Certificate

active

06714083

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase locked loop (hereinafter referred to as “PLL”) circuit and, in particular, to a lock detector that always detects and outputs as to whether a phase difference between an input signal and an output signal is not more than a predetermined value.
2. Description of the Background Art
On a PLL circuit, it takes much time that the phase of a returning output signal is synchronized with the phase of an input signal. Therefore, in order to detect whether the phase difference between the input signal and the returning output signal is not more than a predetermined value, a lock detector monitoring phase synchronization is usually disposed on the PLL circuit. Disposing the lock detector also enables detecting as to whether the phase difference exceeds the predetermined value due to disturbance and the like, during the operation of the PLL circuit.
As a conventional PLL circuit with a lock detector, there is a technology disclosed in Japanese Patent Application Laid Open No. 10-70457 (1998).
FIG. 18
illustrates the configuration of this PLL circuit.
Referring to
FIG. 18
, this PLL circuit comprises: a phase comparator
1
that performs a phase comparison between an input signal f
1
and a feedback signal f
2
that is a divided output signal; a charge pump circuit
2
that changes the pulse width according to the output of the phase comparator
1
, and outputs pulse; a loop filter circuit
3
that integrates the output pulse of the charge pump circuit
2
, and outputs the result as an analog voltage signal Vc; a voltage-controlled oscillator
4
that changes the oscillation frequency according to the value of the analog voltage signal Vc, and outputs an output signal fo; a frequency divider
5
that divides the output signal fo, and outputs a feedback signal f
2
; and a lock detector
9
that detects whether the input signal f
1
and the feedback signal f
2
are in phase synchronization, based on output signals Pu and Pd from the phase comparator
1
.
The voltage-controlled oscillator
4
is formed by a ring counter, for example. The analog voltage signal Vc from the loop filter
3
is applied to the ring counter, and the oscillation frequency of the ring counter changes according to the value of the analog voltage signal Vc.
On this PLL circuit, the feedback signal f
2
is controlled so as to be synchronized with the input signal f
1
. When the phase of the feedback signal f
2
is behind of the phase of the input signal f
1
, a pulse signal of a width corresponding to such a phase difference is outputted from the phase comparator
1
, as a pulse signal Pu. At this time, the value of the analog voltage signal Vc increases by the functions of the charge pump circuit
2
and loop filter
3
. Upon receipt of this analog voltage signal Vc, the voltage-controlled oscillator
4
functions to increase the frequency of the output signal fo and hasten the phase of the feedback signal f
2
.
On the other hand, when the phase of the feedback signal f
2
is ahead of the phase of the input signal f
1
, a pulse signal of a width corresponding to such a phase difference is outputted from the phase comparator
1
, as an output signal Pd. At this time, the value of the analog voltage signal Vc decreases by the functions of the charge pump circuit
2
and loop filter
3
. Upon receipt of this analog voltage signal Vc, the voltage-controlled oscillator
4
functions to decrease the frequency of the output signal fo and delay the phase of the feedback signal f
2
.
As used herein, the output signal Pu of the phase comparator
1
is a pulse signal that changes to “Hi” (assuming “Hi-active” in the description) at the rise of the pulse of the input signal f
1
. The output signal Pd of the phase comparator
1
is a pulse signal that changes to “Hi” (assuming “Hi-active” in the description) at the rise of the pulse of the feedback signal f
2
. One of the output signals Pu and Pd which changes to “Hi” at a later time, falls to “Low” immediately after the mentioned rise, and the other changes to “Low” together with the fall of the former.
The lock detector
9
comprises an exclusive NOR circuit
6
on which, upon receipt of the output signals Pu and Pd from the phase comparator
1
, the exclusive OR of the two signals is inverted and outputted; a delay circuit
7
on which the output signal Pc of the exclusive NOR circuit
6
is delayed and outputted; and a D-flip-flop circuit
8
. The D-flip-flop circuit (hereinafter referred to as “D-FF”)
8
comprises a clock input terminal T to which an output signal Pc of the exclusive NOR circuit
6
is inputted; a signal input terminal D to which an output signal Pa of the delay circuit
7
is inputted; and an output terminal Q from which a lock detecting signal SL is outputted.
The delay circuit
7
is formed by a ring counter, for example. An analog voltage signal Vc from the loop filter
3
is applied to the ring counter. The delay amount of respective delay stages forming the ring counter changes depending on the value of the analog voltage signal Vc.
FIGS. 19 and 20
are diagrams illustrating timing charts of signals in the respective parts of this PLL circuit.
FIG. 19
shows the case that the phase of the input signal f
1
is ahead of the phase of the feedback signal f
2
(i.e., an asynchronous case).
FIG. 20
shows the case that phase of the input signal f
1
substantially coincides with the phase of the feedback signal f
2
(i.e., a synchronous case).
Regardless of whether the feedback signal f
2
and input signal f
1
are delayed or not, the exclusive NOR circuit
6
generates and outputs a pulse signal Pc having a pulse width Pw
1
that corresponds to the phase difference between the two signals, by using the output signals Pu and Pd of the phase comparator
1
(It is supposed to be substantially synchronous in
FIG. 20
, however, assume there is a slight phase difference in the rise of the output signals Pu and Pd). The delay circuit
7
outputs a pulse signal Pa that is behind of the pulse signal Pc by a predetermined time Td
1
.
The D-FF circuit
8
fetches the state of a pulse signal Pa when the pulse signal Pc transits from “Low” to “Hi”, and it outputs, as a lock detecting signal SL, “Hi” when the pulse signal Pa is “Hi”, and “Low” when the pulse signal Pa is “Low”.
If a pulse width Pw
1
of the pulse signal Pc is larger than a delay time Td
1
of the delay circuit
7
, the pulse signal Pa is in “Low” level at t
0
at which the pulse signal Pc transits from “Low” to “Hi” level. Therefore, the D-FF circuit
8
fetches the “Low” state, and outputs the “Low” level indicating that phase is asynchronous, as a lock detecting signal SL.
If the pulse width Pw
1
of the pulse signal Pc is smaller than the delay time Td
1
of the delay circuit
7
, the pulse signal Pa is in “Hi” level at t
1
at which the pulse signal Pc transits from “Low” to “Hi” level. Therefore, the D-FF circuit
8
fetches “Hi” state, and outputs “Hi” level indicating that phase is synchronous, as a lock detecting signal SL.
Thus, the lock detector
9
detects phase synchronous or asynchronous, based on the delay time Td
1
.
FIG. 21
is a circuit diagram illustrating a configuration of a phase comparator
1
disclosed in Japanese Patent Application Laid Open No. 56-169931 and U.S. Pat. No. 4,322,643. The phase comparator
1
is made up of inverter circuits
40
to
43
, two-input NAND circuits
46
to
51
, three-input NAND circuits
52
,
53
, and a four-input NAND circuits
56
. In this circuit configuration, when an input signal f
1
and a feedback signal f
2
are both in “Low” state, output signals Pu and Pd are both in “Low” state.
When an input signal f
1
firstly transits from “Low” to “Hi”, signal change propagates in the following order: the inverter circuits
40
, two-input NAND circuit
46
, three-input NAND circuit
52
, and inverter circuit
42
, so that the output signal Pu transits from “Low” to “Hi”. After transition of the input signal f
1
, when a feedback signal f
2
transits from

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