Lock detection circuit for a phase locked loop circuit

Details Lock detection circuit for a phase locked loop circuit Lock detection circuit for a phase locked loop circuit

2001-11-06

2004-07-13

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C331SDIG002

Reexamination Certificate

active

06762631

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit technology. The present invention provides an improved lock detection circuit that indicates when an output phase is locked to an input phase in a phase locked loop circuit.
BACKGROUND OF THE INVENTION
Phase locked loop circuits are well known.
FIG. 1
illustrates a block diagram of a prior art frequency synthesizer charge pump phase locked loop (PLL) circuit
100
. Input signal FIN is provided to input divider
110
and the output of input provider
110
is provided to a first input of phase frequency detector
120
. Phase frequency detector
120
provides an “up” signal (designated “UP”) and a “down” signal (designated “DN”) to charge pump
130
. As is well known in the art, the UP signal closes a switch to cause current source
140
to provide current I
up
to the output line of charge pump
130
. The DN signal closes a switch to cause current source
150
to draw current I
DN
from the output line of charge pump
130
.
The output line of charge pump
130
is coupled to loop filter
160
and to voltage controlled oscillator
170
. The currents from charge pump
130
adjust the phase of the voltage controlled oscillator
170
. The output signal For from voltage controlled oscillator
170
is provided to feedback divider
180
. The output of feedback divider
180
is provided to a second input of phase frequency detector
120
.
A charge pump PLL is a negative feedback system that insures that the phase difference as well as the frequency difference at the input of phase frequency detector
120
is near zero under steady state conditions. A PLL in such a state is said to be in a “lock” condition or “locked.” The input and output frequencies are related by a fixed ratio which can be selected by choosing the values of the input divider
110
and the feedback frequency divider
180
.
A charge pump PLL is typically a second order system. Therefore, any change from the steady state condition will result in a transient response that is typically characterized by the damping factor and the natural frequency of the system. The damping factor and the natural frequency of the system are dependent upon physical quantities such as the charge pump current, the effective gain of the voltage controlled oscillator
170
, parameters of the loop filter
160
, and properties of the phase frequency detector
120
. The settling behavior of the transient response may also be governed by the comparison frequency at the input of the phase frequency detector
120
.
Because some of these parameters are not constant, the time required for the PLL to acquire lock will vary. The output frequency of the PLL before it acquires lock is not stable and should therefore not be used. Because the charge pump PLL is second order system, there will be some overshoots and some undershoots in the transient response signal.
A lock detection circuit can be constructed that is capable of indicating the locked or unlocked state of the PLL circuit. Various methods exist for implementing a lock detection circuit. The implementation may be either analog or digital. Most prior art implementations rely on monitoring the activity at the output of the phase frequency detector
120
and some sort of analog filtering. For a lock detection signal to be of practical use, the signal should remain stable, should be insensitive to various mismatches in the loop, and should be tolerant to noise, and should have minimum latency.
The output of a Type IV phase frequency detector in a charge pump PLL comprises pulses at the UP output pin and at the DN output pin such that the difference in the pulse widths of the UP signal and the DN signal is equal to the input phase difference. The UP and DN signals are provided to charge pump
130
. In response, charge pump
130
dumps an equivalent charge to adjust the phase of the voltage controlled oscillator
170
. In a locked state, the output of phase frequency detector
120
comprises narrow pulses of equal duration on the UP output pin and on the DN output pin. The use of narrow pulses even in the locked state prevents the formation of a dead zone for small phase differences at the input of phase frequency detector
120
.
There are deviations from ideal behavior in a practical system. For example, the “up” current I
up
and the “down” current I
DN
in charge pump
130
are not exactly equal due to the finite output impedance of current source
140
and current source
150
. There can also be delay mismatches between the UP signal and the DN signal at the output of phase frequency detector
120
. Leakage in loop filter
160
may also affect the operation of the charge pump PLL system.
Because the charge pump PLL system is a negative feedback system, the PLL corrects for all the non-ideal conditions by having a small phase offset at the input of the phase frequency detector
120
of an appropriate magnitude and polarity to negate these effects. This phase difference at the input of the phase frequency detector
120
is called the “static phase error.”
Random noise from individual components within the PLL circuit or from the power supply (not shown) could lead to an occasional pulse (or pulses) at the output of the phase frequency detector
120
. An occurrence of such a pulse (or pulses) does not technically amount to an unlocked condition. Unless proper care is taken in designing a lock detection circuit, such a pulse (or pulses) may appear as an erroneous signal or glitch in the “lock” signal.
It would be desirable to have a lock detection circuit in a phase locked loop circuit that is capable of detecting when an output phase is locked and is not locked to an input phase in the phase locked loop circuit.
It would also be desirable to have a lock detection circuit in a phase locked loop circuit that is capable of generating a lock signal that is stable.
It would also be desirable to have a lock detection circuit in a phase locked loop circuit that is capable of generating a lock signal that is insensitive to mismatches within individual circuit elements within the phase locked loop circuit.
It would also be desirable to have a lock detection circuit in a phase locked loop circuit that is tolerant of noise and that has minimum latency.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for providing a lock detection circuit in a phase locked loop circuit that is capable of detecting when an output phase is locked to an input phase in the phase locked loop circuit, and when an output phase is not locked to an input phase in the phase locked loop circuit.
An advantageous embodiment of the present invention comprises an exclusive OR gate, a deglitch unit, a gate circuit, a count lock circuit, a count unlock circuit, and a D flip flop circuit. The exclusive OR gate receives an UP signal and a DN signal from a phase frequency detector. The exclusive OR gate filters out those portions of an UP signal and those portions of a DN signal that occur at the same time. The output of the exclusive OR gate represents either (1) a portion of an UP signal that occurs when a DN signal is not present, or (2) a portion of a DN signal that occurs when an UP signal is not present.
The deglitch unit outputs a clear “clr” signal pulse only when the UP and DN signals are mismatched in time by more than a predetermined period of time. The delay time is equal to (or slightly greater than) the estimated static phase error of the PLL when it is locked.
The detection of a locked or an unlocked state within the PLL is made by processing “dclr” l signal pulses. The “clr” signal pulses are coupled to a first input of gate circuit and also are coupled to a count unlock circuit. When the PLL is not in a locked condition, the gate circuit passes each “clr” signal pulse to a count lock circuit to reset a counter within the count lock circuit that is counting clock cycles. In the absence of a “clr” signal pulse for a fixed number of clock cycles, the count lock circuit determines that the PLL is locke

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