Lock detection circuit

Details Lock detection circuit Lock detection circuit

2002-04-09

2004-09-21

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S017000

Reexamination Certificate

active

06794944

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lock detection circuit, more specifically to a lock detection circuit provided with counters.
2. Description of the Prior Art
In recent years, attention has been given to a lock detection circuit using a counter for detecting a lock state of a Phase Locked Loop (PLL) circuit. For example, Japanese Published Unexamined Patent Application No. Hei 10-322200 discloses, as shown in
FIG. 8
, a phase lock detection circuit in which a count period generation circuit generates a count period from an input reference signal, a counter counts output signals of a PLL circuit during the count period, and a comparison circuit compares count values.
In a prior art PLL circuit
130
, as shown in
FIG. 9
, an input reference signal RCLK (a frequency fR)
137
from outside is divided by a frequency divider
136
so that its frequency is 1/M of that of the input reference signal (a frequency fM). The M frequency division signal MCLK is a reference signal which is one of two inputs to a phase comparator
131
. A comparison signal which is the other input to the phase comparator
131
is an N frequency division signal NCLK (a frequency fN) obtained by dividing an output signal OCLK (a frequency fOUT)
138
from the PLL circuit
130
using a frequency divider
135
so as to provide a frequency of 1/N. The phase comparator
131
inputs as a reference signal and a comparison signal an M frequency division signal corresponding to a reference signal inputted to the PLL circuit
130
and an N frequency division signal corresponding to an output signal from the PLL circuit
130
, and detects a phase difference between both signals to output phase comparison result signals UP/DOWN corresponding to the phase difference. A charge pump
132
charges a capacitance (not shown; it may be a capacitance in a loop filter) while the UP signal from the phase comparator
131
is active and discharges the capacitance when the DOWN signal is active. The charge pump
132
is turned off when both the UP pulse and the DOWN pulse are inactive. A loop filter
133
flattens an output signal of the charge pump
132
. Its output voltage is supplied as a controlled voltage to a voltage controlled oscillator (VCO)
134
. The VCO
134
outputs a signal which changes an oscillation frequency corresponding to a direct current voltage of the output of the loop filter
133
. This signal becomes the output signal OCLK from the PLL circuit
130
. The output signal OCLK is inputted to the N frequency divider
135
. The N frequency division signal NCLK in which the frequency of the output signal OCLK is divided to be 1/N is inputted as a feedback signal to the phase comparator
131
. The M frequency divider and the N frequency divider need not be provided when M=1 and N=1. A PLL circuit not having the M frequency divider
136
or the N frequency divider
135
may exist.
A count period generation circuit
142
inputs the input reference signal
137
to the PLL circuit
130
to generate a count period signal pulse synthesized therewith having a pulse length of a predetermined multiple of its cycle. An output signal counter
144
uses the count period signal pulse as an enable signal to count the number of waves (the number of cycles) of the output signals
138
outputted from the PLL circuit
130
during the pulse period. To a count value comparison circuit
148
, is set a predetermined reference count value based on design values of the time length of the count period signal pulse and a frequency conversion ratio in the PLL circuit
130
. A lock decision circuit
146
decides a phase lock state between the input and output signals of the integrated PLL circuit
130
from a difference between a reference count value and an output count value measured in the output signal counter
144
.
The lock detection circuit which uses a counter to count output signals of the PLL circuit during a predetermined count period, and then compares it with a reference count value to detect lock/unlock has the problem that the time to detect the lock state or the unlock state may be longer than required. The reason is as follows.
In the prior art lock detection circuit shown in
FIG. 8
, until the count period generated in the count period generation circuit
142
is terminated, the count value comparison circuit
148
cannot compare a count value of the number of waves of the output signals OCLK with the reference count value and can decide the lock or unlock state only during each count period generated in the count period generation circuit
142
. In other words, the comparison operation of the counter for deciding the lock state is performed once during each count period. When the lock state is changed to the unlock state, the unlock state is detected after the count period similar to that of the lock state decision.
In this manner, in the prior art lock detection circuit, one counter counts output signals over the same count period to detect lock or unlock so that the lock detection time and the unlock detection time cannot be set to an optimal value.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a lock detection circuit which optimizes the lock detection time and the unlock detection time of a PLL circuit.
According to an aspect of the present invention to provide means for solving the foregoing problems, a lock detection circuit has a phase comparison circuit for comparing the phases of a reference signal and a feedback signal based on an output signal to output a comparison result; an oscillation circuit for changing an oscillation frequency of the output signal based on the comparison result; and a detection circuit for detecting that coincidence of a frequency of the feedback signal and a frequency of the reference signal is maintained during a predetermined period to allow a lock signal to be active.
A high precision lock signal can be thus generated using a digital value of a frequency.
According to another aspect, a lock detection circuit has a first counter for inputting and counting the feedback signals inputted to the one input terminal of a phase comparator of a PLL circuit; a second counter for inputting and counting the reference signals inputted to the other input terminal of the phase comparator; a third counter for performing a count operation when a count value of the first counter coincides with a predetermined first value and a count value of the second counter coincides with the first value; and a decision circuit for outputting a signal showing a lock state when a count value of the third counter coincides with a predetermined second value.
According to the present invention, the lock detection circuit may have a comparison circuit for outputting a signal in a state showing coincidence when a count value of the first counter coincides with a predetermined first value and a count value of the second counter coincides with the first value, wherein the third counter inputs the signal outputted from the comparison circuit as a signal to control a count operation, is allowed to be in a count enable state when the signal outputted from the comparison circuit is in a state showing the coincidence, and counts the feedback signals inputted to the third counter.
According to the present invention, the comparison circuit resets the third counter when a count value of the first counter reaches a predetermined first value and a count value of the second counter is not the first value, and the decision circuit outputs an output signal of a value showing an unlock state when a count value of the third counter is reset. As is apparent in the description below, the foregoing problems can be solved by claims of the present invention likewise.


REFERENCES:
patent: 5126690 (1992-06-01), Bui et al.
patent: 5394444 (1995-02-01), Silvey et al.
patent: 5400034 (1995-03-01), Smith
patent: 5870002 (1999-02-01), Ghaderi et al.
patent: 6259290 (2001-07-01), Takada et al.
patent: 6429901 (2002-08-01), Kiyose et al.
patent: 10-32220

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