Lock detecting circuit for phase-locked loop frequency synthesiz

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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331 17, 331 25, 331DIG2, H03L 718

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044370725

ABSTRACT:
A phase-locked loop circuit comprising a reference oscillator (1), a reference frequency divider (2) for dividing the output signal of the reference oscillator, a programmable frequency divider (3), a phase comparator (4) for monitoring the difference in phase between the output signal of the two frequency dividers, a lock detector (11) for generating a first signal which is pulse-shaped or rectangular when the above-mentioned difference in phase is generated, and a digital signal maintaining circuit (100) for converting the first signal into a second directed current signal.

REFERENCES:
patent: 3982190 (1976-09-01), Schaefer
patent: 4122405 (1978-10-01), Tietz et al.
patent: 4290029 (1981-09-01), Streckenbach
Akiyama et al., "PLL IC Capable of Direct Division of FM Local Oscillator Frequency", IEEE Transactions on Consumer Electronics, vol. CE-26, Feb. 1980, pp. 36-41.
Blatter et al., "Frequency Synthesis Custon LSI: The Inside Story", IEEE Transactions on Consumer Electronics, vol. CE-24, Aug. 1978, pp. 429-434.
Sharpe, "How can you be sure that your PLL is really locked in?", Electronic Design News, vol. 22, Feb. 20, 1977, pp. 109-111.
European Published Patent Application No. 0,012,899, Published Jul. 9, 1980, Inventor: Streckenbach, (Equivalent to U.S. Pat. No. 4,290,029).

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