Lock detect circuit for a phase locked loop

Details Lock detect circuit for a phase locked loop Lock detect circuit for a phase locked loop

2008-01-29

2008-01-29

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C331SDIG002, C327S007000, C327S157000

Reexamination Certificate

active

11254569

ABSTRACT:
An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.

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Nosaka, Hideyuki, et al., “A 39-to-45-Gbit/s Multi-Data-Rate Clock and Data Recovery Circuit With a Robust Lock Detector,” IEEE Journal of Solid-State Circuits, vol. 39, No. 8, Aug. 2004, pp. 1361-1365.

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