Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-03-29
2002-12-10
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S344000, C438S291000, C438S302000, C438S305000
Reexamination Certificate
active
06492670
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with pocket regions.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), CMOS fabrication processes have utilized a two-dimensional channel-doping technique. With reference to
FIG. 1
, a conventional MOSFET
110
is provided on a portion
112
of an integrated circuit. MOSFET
110
is provided between insulation regions
114
and includes a source
116
, a drain
118
, and a gate structure
120
. Gate structure
120
includes spacers
122
, a dielectric layer
124
, and a gate conductor
127
.
Dielectric layer
124
is provided between and partially over a source extension
126
and a drain extension
128
(e.g., above a channel region
130
). A silicide layer
132
is formed over gate conductor
127
, source
116
, and drain
118
. Channel region
130
does not include a two-dimensional doping implant, wherein the channel-doping profile in the lateral direction is non-uniform and the channel-doping profile in the vertical direction is a super-steep retrograded channel-doping profile. The two-dimensional channel-doping profile is critical to scaling (i.e., proportional operation and structural elements in the ultra-small dimensions of MOSFET
110
).
MOSFET
110
includes shallow pocket regions
134
and
136
which effectively suppress the short-channel effect (which degrades the robustness of the transistor to random process variations). Shallow pocket regions
134
and
136
are provided in a conventional CMOS pocket implant process. The implant process is performed after gate structure
120
is fabricated and before layer
132
is formed. Regions
134
and
136
are not deeper than source
116
and drain
118
. Regions
134
and
136
are formed before extensions
126
and
128
, regions
116
and
118
, and spacers
122
.
Pocket regions
134
and
136
should be deep enough to suppress punch through effect. However, with conventional processes, regions
134
and
136
cannot be made deep enough without forming a “halo-like structure”. The disadvantages “halo-like structure” are discussed below with reference to FIG.
2
.
With reference to
FIG. 2
, a MOSFET
134
is substantially similar to MOSFET
110
, as discussed with reference to FIG.
1
. However, MOSFET
134
includes deep pocket implant regions
135
and
137
. Channel
130
includes a two dimensional doping implant, wherein the channel-doping profile in the lateral direction is not uniform, and the channel-doping profile in the vertical direction is a super-steep retrograded channel-doping profile. Implants
135
and
137
are formed after extensions
126
and
128
, drain
116
, source
118
, and spacers
122
in a conventional process. The pocket implant associated with regions
135
and
137
results in a “halo-like” structure around the border of regions
116
and
118
located proximate channel region
130
.
The halo-like structure of pocket regions
135
and
137
(
FIG. 2
) increases the doping concentration near the junction of source
116
and drain
118
. Increased doping concentration near the junction of source
116
and drain
118
degrades (i.e., increases) the source/drain junction capacitance (e.g., parasitic capacitance) and, hence, reduces the speed of MOSFET
134
.
Thus, there is a need for a method of forming deeper pocket regions which do not have a halo-like structure. Further still, there is a need for transistors that have locally confined deep pocket regions. Even further still, there is a need for an efficient method of manufacturing deep pocket regions for a transistor having a two-dimensional channel profile.
SUMMARY OF THE INVENTION
The present invention relates to a method of manufacturing an integrated circuit. The integrated circuit includes a gate structure between a source region and a drain region in a semiconductor substrate. The gate structure includes a plurality of dielectric spacers. The method includes removing the dielectric spacers, thereby exposing the semiconductor substrate at a first location and a second location, and providing an ion implant at the first location and at the second location. The ion implant forms deep pocket regions.
The present invention further relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having locally confined deeper pocket regions. The method includes steps of forming at least part of a gate structure on a top surface of a semiconductor substrate and between a source and a drain. The gate structure includes a spacer. The method also includes forming a silicide over at least the source and the drain, removing the spacer, and providing a dopant at a location associated with the spacer. The dopant forms the locally confined deeper pocket region.
The present invention still further relates to a process for forming a first pocket region at least partially below a shallow source extension and a second pocket region at least partially below a shallow drain extension. The process includes forming a plurality of gate structures on a top surface of a substrate, stripping dummy spacers associated with the gate structure to form openings to the substrate, and providing a dopant through the openings to the substrate. The dopant forms the first pocket region and the second pocket region.
The present invention also relates to an integrated circuit including a transistor. The transistor has a gate structure on a top surface of a semiconductor substrate and is disposed between a source and a drain. The transistor includes a first pocket region and a second pocket region. The first pocket region extends below the drain. The second pocket region extends below the source. The first pocket region meets the second pocket region under a channel.
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Advanced Micro Devices , Inc.
Nelms David
Tran Mai-Huong
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