Locally boosted top plate sampling for a sampling capacitor

Details Locally boosted top plate sampling for a sampling capacitor Locally boosted top plate sampling for a sampling capacitor

2008-10-10

2010-10-19

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C341S122000

Reexamination Certificate

active

07816951

ABSTRACT:
An analog sampling network (100) includes a sampling capacitor being coupled between a bottom plate sampling switch and a top plate sampling switch implemented as NMOS transistors. The top plate sampling switch has source/drain terminals coupled respectively to the sampling capacitor and a first reference voltage. The analog sampling network includes a top plate boosting circuit (150) providing a boosted gate voltage to a gate terminal of the top plate sampling switch during a sampling phase, the boosted gate voltage being the sum of a first voltage and a second voltage. The first voltage is approximately equal to the first reference voltage and tracks process, temperature, power supply voltage and biasing condition variations. The second voltage is a maximum operating voltage from the gate to drain/source terminal for a fabrication process used to fabricate the second MOS transistor.

REFERENCES:
patent: 6329848 (2001-12-01), Maes et al.
patent: 7372319 (2008-05-01), Lee
patent: 7453291 (2008-11-01), Song
patent: 7532042 (2009-05-01), Lee
patent: 7583110 (2009-09-01), Butler
patent: 7626622 (2009-12-01), Kasuga et al.

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