Localized heating for defect isolation during die operation

Details Localized heating for defect isolation during die operation Localized heating for defect isolation during die operation

1999-08-10

2002-11-19

Nguyen, Vinh P. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

06483326

ABSTRACT:

FIELD OF THE INVENTION
The present device relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving defect isolation.
BACKGROUND OF THE INVENTION
The electronics industry continues to rely upon advances in semiconductor technology, including integrated circuits, to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. In addition, many of the individual devices within the wafer are being manufactured with smaller physical dimensions. As the number of electronic devices per given area of the silicon wafer increases, and as the size of the individual devices decreases, testing processes become more important and more difficult.
Many defects in integrated circuits can recover or fail at higher temperatures. For instance, circuit sites exhibiting temperature sensitive defects, such as charge trapping and ionic contamination, can recover when heated. Traditionally, isolation of defective sites has been attempted by heating the entire device during extensive electrical testing. Such electrical testing, however, does not always work. Moreover, even if a unique node is electrically identified, the physical defective site usually cannot be identified.
Semiconductor technology would benefit from a practical method and apparatus for heat testing integrated circuits for isolation of defective sites.
SUMMARY OF THE INVENTION
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to an example embodiment, the present invention is directed to a method for testing a semiconductor die. The semiconductor die has circuitry on one side and silicon on an opposite side. The opposite side is thinned. The die is powered via a power supply, and heat is directed via the opposite side to a portion of the circuitry. The circuitry is monitored, and a circuit that reacts to the heat is detected therein.
According to another example embodiment, the present invention is directed to a system for testing a semiconductor die. The die has circuitry on one side and silicon on an opposite side. The system includes a first means for thinning the opposite side, a second means for directing heat via the opposite side to a portion of the circuitry, and a third means for monitoring the circuitry and detecting therein a circuit that reacts to the heat. The first and second means are optionally implemented using the same tool, e.g., a laser.
According to yet another example embodiment, the present invention is directed toward a system for testing a semiconductor die having circuitry on one side and silicon on an opposite side, wherein the opposite side is AR coated. The system includes a milling machine for thinning the opposite side, a laser arrangement for directing heat via the opposite side to a portion of the circuitry, and a microscope for monitoring the circuitry and detecting therein a circuit that reacts to the heat.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.


REFERENCES:
patent: 4698587 (1987-10-01), Burns et al.
patent: 5414370 (1995-05-01), Hashinaga et al.
patent: 5430305 (1995-07-01), Cole, Jr. et al.
patent: 5493236 (1996-02-01), Ishii et al.
patent: 5523694 (1996-06-01), Cole, Jr.
patent: 5708371 (1998-01-01), Koyama
patent: 5804980 (1998-09-01), Nikawa
patent: 5844416 (1998-12-01), Campbell et al.
patent: 5952837 (1999-09-01), Koyama
patent: 6028435 (2000-02-01), Nikawa
patent: 6066956 (2000-05-01), Nikawa
patent: 6391664 (2002-05-01), Goruganthu
Joseph, T., Berry, A., and Bossmann, B., Infrared Laser Microscopy of Structures on Heavily Doped Silicon, ISTFA, Oct., 1992, pp. 1-7.
Cole, Jr., Edward I., Tangyunyong, Paiboon, and Barton, Daniel L.,Backside Localization of Open and Shorted IC Interconnections, 1998, pp. 129-136 (Month unavailable).
Poate, J. M. and Mayer, James W., editors,Laser Annealing of Semiconductors, 1982, pp. 43-47 (Month unavailable).
Infrared Microscopy of Doped Silicon: Zeiss 321IR; ISTFA p.1 (1992) (Month unavailable).
Laser Thermal Effects: Sandia Report “AMD SOM/Laser Thermal Stimulation of Front and Backside Timing Paths” Sep. 4, 1998 Sandia AMD CRADA Team.

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