Local self-boost inhibit scheme with shielded word line

Details Local self-boost inhibit scheme with shielded word line Local self-boost inhibit scheme with shielded word line

2007-10-10

2010-06-22

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185030, C365S185240, C365S185260, C365S085000

Reexamination Certificate

active

07742338

ABSTRACT:
A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent word lines and applying the same voltage to each in array access operations. This allows each word line of the set or pair to shield the other from word line to word line capacitive voltage coupling. In NAND memory string embodiments the various cells of strings of non-volatile memory cells are programmed utilizing modified or unmodified drain-side self boost, source-side self boost, local self boost, and virtual ground programming processes that utilize two or more “blocking” memory cells on either the source line side and drain line side of a selected memory cell. The paired blocking cells shield each other during programming to reduce coupled noise, to prevent charge leakage from the boosted channel of the selected memory cell.

REFERENCES:
patent: 7525841 (2009-04-01), Aritome
patent: 7561469 (2009-07-01), Aritome
patent: 2005/0105334 (2005-05-01), Futatsuyama
patent: 2005/0174852 (2005-08-01), Hemink
patent: 2007/0236992 (2007-10-01), Oowada

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