Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-12-21
2004-07-20
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S513000
Reexamination Certificate
active
06765280
ABSTRACT:
FIELD OF INVENTION
This invention relates generally to semiconductor device isolation. In particular, it relates to local oxidation of a sidewall sealed shallow trench for providing isolation between devices formed in a substrate.
BACKGROUND
Integrated circuits include substrates which generally include active devices formed in proximity to each other. Increasing the density of active devices included on a substrate requires the active devices to be formed more closely to each other. If the active devices are too close to each other, the active devices can electrically connect to each other. Alternatively, signals from one active device can couple to a neighboring active device. This coupling or crosstalk can degrade the performance of the active devices. Therefore, typically some type of isolation structure must be formed between active devices to prevent the active devices from being electrically connected and to prevent coupling of signals between the active devices.
FIG. 1
shows a first type of isolation structure
8
typically used to isolate active devices of a substrate
10
. The isolation structure
8
shown in
FIG. 1
is formed using a local oxidation of silicon (LOCOS) technique. LOCOS isolation structures include the surface of an active semiconductor substrate
10
being oxidized between active device regions
12
,
14
of the semiconductor substrate
10
surface to help prevent electronic interactions between adjacent active device regions
12
,
14
.
The effectiveness of LOCOS isolation structures degrades significantly as the active device regions
12
,
14
become closer together due to parasitic currents that can develop between adjacent devices
12
,
14
beneath the LOCOS structures. Additionally, the LOCOS isolation structure
8
is too wide to allow the active device regions
12
,
14
to be formed too close to each other.
FIG. 2
shows a second type of isolation structure typically used to isolate active device regions
24
,
26
of a substrate
20
. The isolation structure shown in
FIG. 2
is formed by etching a trench
22
in a silicon substrate
20
between the active device regions
24
,
26
, and filling the trench
22
with an isolation material such as silicon oxide. Generally, the deeper the trench
22
, the greater the isolation between the active device regions
24
,
26
. Generally, the narrower the trench
22
, the closer the active device regions
24
,
26
can be with respect to each other. However, if the trench
22
is deep and narrow, the trench
22
can be very difficult to form. That is, deep narrow trenches can be difficult to properly fill with an isolation material.
It is desirable to have a substrate isolation structure which allows active device regions of the substrate to be formed close to each other while still maintaining isolation between the active device regions. It is desirable that the substrate isolation structure provide more isolation between the active device regions than LOCOS isolation and trench isolation structures.
SUMMARY OF THE INVENTION
The present invention is a substrate isolation method and structure which allows active device regions of the substrate to be formed close to each other while still maintaining isolation between the active device regions. The substrate isolation structure provides more isolation between the active device regions than LOCOS isolation and trench isolation structures.
A first embodiment of this invention includes a semiconductor isolation structure. The semiconductor isolation structure includes a substrate. A first device and a second device are formed within the substrate. An isolation region is formed within the substrate between the first device and the second device. The isolation region includes a deep region which extends into the substrate. The deep region includes a deep region cross-sectional area. A shallow region extends to the surface of the substrate. The shallow region includes a shallow region cross-sectional area. The deep region cross-sectional area is greater than the shallow region cross-sectional area.
A second embodiment includes a semiconductor isolation structure. The semiconductor isolation structure includes a substrate. A first device and a second device are formed within the substrate. An isolation region is formed within the substrate between the first device and the second device. The isolation region includes an deep region which extends into the substrate. The deep region includes an oxide. A shallow region extends to the surface of the substrate. The shallow region includes a protective wall. The protective wall can be formed from an oxide and a nitride.
A third embodiment includes a method of forming an isolation structure within a substrate. The method includes forming a trench in the substrate. A protective wall layer is formed within the trench. A bottom portion of the protective wall layer is removed exposing a surface of the substrate. The exposed surface of the substrate is directly oxidized. Finally, the trench is filled with an isolation material. The isolation material can be an oxide.
A fourth embodiment is similar to the third embodiment. The step of removing a bottom portion of the protective wall layer exposing a surface of the substrate of the fourth embodiment includes removing the bottom portion of the protective wall layer exposing the substrate, and forming a second trench in the exposed substrate forming an exposed surface.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 4502913 (1985-03-01), Lechaton et al.
patent: 4551743 (1985-11-01), Murakami
patent: 4685198 (1987-08-01), Kawakita et al.
patent: 5057450 (1991-10-01), Bronner et al.
patent: 5221857 (1993-06-01), Kano
patent: 5686344 (1997-11-01), Lee
patent: 5747866 (1998-05-01), Ho et al.
patent: 5914523 (1999-06-01), Bashir et al.
patent: 5976950 (1999-11-01), DiSimone et al.
Cao Min
Greene Wayne M.
Tavassoli Malahat
Vande Voorde Paul J.
Agilent Technologie,s Inc.
Lee Eddie
Owens Douglas W.
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