Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2005-08-09
2005-08-09
Kebede, Brook (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S762000, C438S622000
Reexamination Certificate
active
06927494
ABSTRACT:
A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels. Furthermore, by allowing these local electrical interconnections to be produced during the same manufacturing step as the macro elements of the integrated circuit, the method of the present invention tends to reduce the number of steps required to produce an integrated circuit.
REFERENCES:
patent: 5366911 (1994-11-01), Lur et al.
patent: 6087677 (2000-07-01), Wu
patent: 6444565 (2002-09-01), Feild et al.
Allman Derryl D. J.
Hightower James R.
Saopraseuth Phonesavanh
Kebede Brook
LSI Logic Corporation
Luedeka Neely & Graham
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