Local ESD protection for low-capacitance applications

Details Local ESD protection for low-capacitance applications Local ESD protection for low-capacitance applications

2007-10-02

2007-10-02

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

10936912

ABSTRACT:
A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.

REFERENCES:
patent: 6388850 (2002-05-01), Ker et al.
patent: 6639772 (2003-10-01), Chuang et al.
patent: 6690557 (2004-02-01), Hung et al.
patent: 2005/0045909 (2005-03-01), Zhang
patent: 2005/0045955 (2005-03-01), Kim et al.

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