Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2007-12-18
2007-12-18
Phan, Trong (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S203000, C365S230060, C365S205000
Reexamination Certificate
active
11271024
ABSTRACT:
A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter than the length of the global digit lines. As a result, the local digit lines have substantially less capacitance so that a voltage stored by a memory cell capacitor can be more easily transferred to the local digit line. The coupling circuits provide current amplification so that the voltage on the local digit lines can be more easily transferred to the global digit lines. A write back circuit is coupled to the local digit line to restore the voltage of the memory cell capacitor.
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Kirsch Howard
Manning H. Montgomery
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Phan Trong
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